19WSC054: Electronic System Design with FPGAs Coursework 2 - Engineering Assignment Help

Assignment Task:

Description

• Aim: This assignment is designed to help you develop further your VHDL programming skills.

• The primary goal of this assignment is to use VHDL and TCL to design and validate a system that integrates a pseudo-random number generator, a memory and an ordering module.

Pseudorandom number generator (PRNG): basic description

• Pseudo and random number generators have applications in gambling, computer simulation, cryptography, and other areas where producing an unpredictable result is desirable. While cryptography and specific numerical algorithms require a very high degree of “apparent” randomness, many other operations only need a modest amount of unpredictability. Aiming to improve its randomness, you are asked to implement a PRNG that integrates the four modules illustrated below:

• Our PRNG integrates two Fibonacci sequence modules and two algorithms.

• PRNGs can employ different implementations that will generate random numbers following distinct distributions. A basic form of randomization can be accomplished by using the procedure uniform from the IEEE math_real package.

• There are other packages (e.g., OSVVM - RandomPkg.vhd) that in addition to the uniform, also provide support for other distributions such as:
– FavorSmall,
– FavorBig,
– normal, and
– Poisson.

System requirements and constraints

• Pseudorandom number generator (PRNG) module
– Your PRNG shall include the 2 Fibonacci sequences and the 2 PRNG algorithms.
– Feel free to implement or use PRNG algorithms available in any library or package (e.g., IEEE math_real).
– The output number signal must be 32 bits.
– Internally you can use as many signals, registers, states or other components you might judge necessary.
– The example below shows a set of signals that are used to obtain the input paraments for the Fibonacci sequences and PRNG algorithm modules.
– The four modules must be able to generate different values range (e.g., a sequence of 5 or 10 or 20 random numbers).

• Memory
– You can either use the memory developed in the lab or rely on the options available on Vivado IP block library.
– The decision of using simple or dual-port memory is up to your implementation.
– The maximum depth of the memory is up to your implementation.

• Ordering number module
– This module shall read and put the read numbers in a certain order.
– Your module shall support two ordering/sorting algorithms. Examples of such algorithms are:
– Merge sort,
– Heapsort,
– Quicksort,
– Shell sort,
– Bubblesort.
– The module internal implementation, as well as its interface, are dependable of your design.

• Validation
– You shall create a testbench to validate the target system.
– Your testbench must support different scenarios.
– You must develop a TCL file to:
– create a project considering your input VHDL files
– create a library, compile and simulate your solution
– list necessary signals in one or more waveforms to explain your validation scenario.
– The validation scenario should consider the generation of, at least, 5 numbers per PRNG component, i.e., 5 (Fibonacci Sequence 1) + 5 (Fibonacci Sequence 2) + 5 (PRNG algorithm A) + 5 (PRNG algorithm B)

Report format and tips

• Your report should not exceed 2 pages in length
– Feel free to use font size 11

• Your report should focus on two key aspects:
– the design development and
– the performance analysis of the validation scenario

• The design development might include, among others:
– block diagram
– description and justification of your design decisions

• The performance analysis might include, among others:
– The performance comparison between both ordering/sorting algorithms. Here you could use, for example, the number of clock cycles that takes to order 20 numbers.

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