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Advanced Computer Architecture - 10-bit Memory - Virtual and Physical Address - IT Assignment Help
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Advanced Computer Architecture Assignment 1
1) A system with 10-bit memory address has a cache with the following properties:
• 2-way set associative
• Uses LRU replacement policy
• The current content of the cache is shown below.
|
Index |
Tag |
V |
B3 |
B2 |
B1 |
B0 |
Tag |
V |
B3 |
B2 |
B1 |
B0 |
|
0 |
04 |
1 |
56 |
3E |
1A |
78 |
0A |
0 |
84 |
5D |
23 |
57 |
|
1 |
07 |
1 |
44 |
23 |
62 |
C2 |
15 |
1 |
93 |
A5 |
3F |
42 |
|
2 |
14 |
0 |
86 |
4A |
B6 |
7D |
12 |
1 |
06 |
A5 |
1D |
25 |
|
3 |
16 |
1 |
33 |
99 |
04 |
61 |
06 |
1 |
61 |
49 |
2E |
94 |
|
4 |
11 |
0 |
82 |
5A |
28 |
75 |
08 |
1 |
65 |
D2 |
1A |
78 |
|
5 |
16 |
1 |
98 |
11 |
14 |
39 |
06 |
0 |
88 |
09 |
62 |
35 |
|
6 |
0A |
1 |
60 |
A4 |
7E |
52 |
05 |
1 |
68 |
79 |
B8 |
70 |
|
7 |
05 |
1 |
07 |
59 |
22 |
49 |
03 |
1 |
63 |
81 |
50 |
60 |
What are the results of the following read operations?
a) Specify whether it is a hit or miss
b) Specify whether there is a replacement or not (if there is replacement specify the block address to be replaced )
c) The value read by the operation (if is determinable from the information given, otherwise just write ND for undeterminable)
Assume that reads are executed in the order given in the table below (addresses are given in hex).
|
Address to be read |
Hit/Miss |
Replace/not |
Value read (or ND) |
|
0x2A6 |
|
|
|
|
0x159 |
|
|
|
|
0x12F |
|
|
|
|
0x2A6 |
|
|
|
|
0x12C |
|
|
|
|
0x0D7 |
|
|
|
|
0x065 |
|
|
|
|
0x087 |
|
|
|
2) We have a byte-addressable computer that has 20-bit virtual addresses and 16-bit physical addresses. Assume a page size of 1KByte.
a) How many bits of each virtual address is the virtual page number?
b) How many bits of each physical address is the physical frame number?
c) How much is the size of the page table for a single process if you have Valid, Dirty and PFN in your page table?
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