Circuit Design Case studies and Algorithms Assignment

Assignment Task

Error Coding

1. Become familiarised with the Altera Quartus Prime electronic circuit design software and model, using VHDL, a serial communications receiver (7/4 decoder), with error control, based on a linear sequential circuit with the transfer function (1 + D² + D³)^-1, as shown in figure
2. Develop the 7/4 decoder VHDL code into a 15/11 decoder with the characteristics (1+ D³ + D⁴)^-1 .
3. Develop the VHDL code for a 7/4 encoder with a characteristic function (1 + D² + D³).
4. Develop the full 7/4 coding Linear Sequential System (LSS) (Transmitter and Receiver)

General Circuit Design Case studies and Algorithms

1. i) Determine the algorithms that convert BIT_VECTORs to INTEGERs and INTEGERs to BIT_VECTORs where the vectors are 5 bits
2. ii) In addition, modify these algorithms assuming the vectors are interpreted as being in 2’s complement form.

1. Write a function called inttovec, which converts a positive integer (in the range 0 to 31) to a 5-bit vector representing this number in Then write\

a function called vectoint which converts a 5-bit vector to an integer. Test these functions using a suitable entity.

1. It is required to build a circuit which counts both the number of people currently in a shop and the number of people that have entered the shop in The signals enter and leave are BITs and the entrance or exit of a customer is indicated by a low to high transition on these signals. Design a shop counter which updates the values of total and no_in and outputs these values as integers. Your design should also check that the circuit does not think a negative number of people are currently in the shop, and if it does, a suitable error message should be produced. (It is anticipated you will have to use ATTRIBUTES). Also include a reset facility that resets both total and no_in to zero when the RESET bit goes high.
2. Use your type conversion functions to allow for the values of total and no_in to be output as BIT_VECTORs.

1. Consider the following 4-stage linear feedback shift register (LFSR)
   1. Firstly, design a unit called lfsr of the type shown below. This unit is made up of a D-type flip-flop with asynchronous reset and one XOR gate (use the models already developed in previous questions). Write the VHDL code for this unit and verify the correctness of your design through

1. Using lfsr as a COMPONENT, derive the VHDL code for the 4-stage LFSR, shown above, by instantiating this module four times. Simulate your solution and check your circuit operates in the correct

1. Consider the engine monitor system shown

The signals speeda and speedb are 6 bit-vectors that represent the speed of two engines- engines A and B respectively - in 100s of revs/minute. Each clock cycle the speeds of both engines are sampled and it is decided whether either of the engine alarm signals should be set high. These signals go high if the most recent sampled engine speed is over 50% lower than the engine speed 9 sample earlier. (That is, if the engine is considered to be decelerating too rapidly, i.e. it has failed).

1. Define a package which contains all the relevant type definitions for the engine monitor and a BIT_VECTOR to INTEGER conversion function.
2. Design an engine monitor entity to the above specification. To simplify the processing, convert the BIT_VECTOR inputs to INTEGERs and carry out all subsequent analysis on these

• Test your engine monitor with an appropriate test

1. Because this module is an important component in a safety-critical system, a further system is required that uses three engine monitors and a majority voting scheme to determine whether an alarm signal should be set. (This will allow for one engine monitor to fail but for the overall system to remain functional). In addition to setting the alarm signal, a suitable warning should be issued if an engine decelerates too rapidly. Design this component and test it using the same test bench as before.

Asynchronous: Schematic Implementation

1. Given the following primitive flow table
   1. List the SS-to-SS paths and construct the adjacency
   2. If any race conditions exist in the flow table, determine if effective row reordering will eliminate race condition(s). If so, make state assignments for a race-free circuit and construct and excitation map.

1. Given the following primitive flow table
   1. Use an implication chart to determine sets of equivalent stable
   2. Eliminate any redundant stable states and construct a non-redundant primitive flow chart.

1. Design an asynchronous dicode encoder system to operate as illustrated in the waveform diagram. The dicode system is designed so that the Data and the Clock signals do not change state at the same time giving a FMC (Data changes before the Clock). On the positive Clock edge the system will give a SET output signal if the Data input has changed from a 0 to a 1 (first half of clock period set to 1 and second half to 0). The system will give a RESET output signal if the Data input has changed from a 1 to a 0 (first half of clock period set to 0 and second half to 1). If the Data input has not changed condition between successive clock edges then the Output remains at

In order to assist the design process the system states have been identified as (a to i) in the waveform diagram. Start the design by developing the Primitive Flow Table, remove redundant groups (if applicable), develop the merger and adjacency diagram etc.

1. Design an clock signal splitter asynchronous system which will take an input clock signal and output two signals where each one gives an alternate 1 pulse extracted from the clock signal, as shown in the waveform diagram below

In order to assist the design process the system states have been identified as (a to d) in the waveform diagram. Start the design by developing the Primitive Flow Table, remove redundant groups (if applicable), develop the merger and adjacency diagram etc.

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