CIS 480-580: Computer Architecture Project MIPS Simulator - IT Computer Science Assignment Help

Assignment Task:

Task:

1. Objectives

This project is designed to help students to understand the pipelining on a RISC architecture (MIPS), pipeline hazards, and hazards mitigation techniques including forwarding and stalling. Students will gain programming experience in C.

2. Goals Your team of 2 students will build a simulator of a (5-stage pipelined) MIPS in C. This simulator will read a binary executable file containing a sequence of MIPS instructions and simulate their execution in stages in a (pipelined) MIPS processor.

Project 1 is a non-pipelined MIPS.

Project 2 is a pipelined MIPS without the considerations for branch hazard and data forwarding.

Project 3 is a pipelined MIPS including branch hazard and data forwarding. Due dates for Project 1, 2 and 3 are October 6, October 29 and November 17, respectively.

3. Specification

3.1 Input Your simulator will read a binary executable file. It is of size 1KB and consists of 512B of data segment followed by 512B of text segment (offset 0x200). Do not try to open this file as it causes an error. Assume big-endian. Assume input files do not contain any errors.

3.1.1 Registers The user can use any of the 32 MIPS registers (0-31). Please note that $0 is read-only and should always contain the value 0. Your simulator will need to include a register file (e.g., an array of 32 integers) that maintains the values of all the 32 registers and updates the registers as the instructions are executed.

3.1.2 Data segment The data segment is of 512B and the only form of data will be integer numbers (4 bytes long). I.e., there can be at maximum 128 integer data in the data segment. The data will not contain any other form of data such as string (ascii characters) or floating point numbers. When the program sees load or store instructions, the address will resolve to access one of these 128 integer data. Therefore, as execution proceeds, loads (lw) can read from the data segment and stores (sw) can write to the data segment.

3.1.3 Text segment The text segment is of 512B, i.e., there can be at maximum 128 MIPS instructions because each MIPS instruction is 4 bytes long. However, due to the presence of branches and jumps, some instructions will be executed multiple times. The text segment will only contain the following MIPS instructions.

The above CIS 480-580: IT Assignment has been solved by our  IT Assignment  Experts at My Uni Paper. Our Assignment Writing Experts are efficient to provide a fresh solution to this question. We are serving more than 10000+ Students in Australia, UK & US by helping them to score HD in their academics. Our experts are well trained to follow all marking rubrics & referencing style.

Be it a used or new solution, the quality of the work submitted by our assignment experts remains unhampered. You may continue to expect the same or even better quality with the used and new assignment solution files respectively. There’s one thing to be noticed that you could choose one between the two and acquire considered worthy of the highest distinction.