COMP 30002: Different Computer Architectures and Hardware - Conflict in the Pipeline - Computer Science Assignment Help

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Assignment Task :

Module Learning Outcomes
The following LOs are achieved by the student by completing the assignment successfully

  • Analyze an awareness of specialized architectures which offer high performance for particular applications areas. 
  • Develop independent learning skills and be able to learn more about different computer architectures and hardware.  

 

Assignment Objective
The aim of this assessment is to assess student’s awareness on different types of pipeline coflicts and how to resolve each type of conflicts. Also to assess student’s knowledge on different computer architectures and hardware.

 

Assignment Tasks

1. Consider the following pipeline, each segment in the pipeline is represented by Sk and performs some operation (Opcode operand1, operand2, operand3) at given time Tk.

Input

 

a. Discuss by giving reasons the type of conflict which will be occurring, if following are the details about the given pipeline. Discuss ways to avoid/resolve the conflict in the pipeline.
S1: T8: ADD R1, A, D
S2: T8: MUL R5, R1, B
S3: T8: DIV R6, R5, C  

b. Discuss by giving reasons the type of conflict which will be occurring, if following are the details about the given pipeline. Discuss ways to avoid/resolve the conflict in the pipeline.
S1: T3: DIV R5, X, Y
S2: T5: MUL R6, R5, Z
S3: T7 SUB R7, R6, W (10 Marks)

c. Discuss by giving reasons the type of conflict which will be occurring, if following are the details about the given pipeline. Discuss ways to avoid/resolve the conflict in the pipeline.
S1: T4: JUMP 110
S2: T4: BRANCH 101
S3: T4: CALL 010

 

2. Consider any five I/O devices of your choice. Based on the type of I/O device, assign some suitable priority to each I/O device considered. Each I/O device can raise interrupt for the CPU at any time for doing Input/Ouput. Discuss in detail with a suitable diagram how priority interrupt can be managed between choosen I/O devices and CPU when using following methods:
a. Daisy-chaining priority interrupt 
b. Polling 
c. Give your reflection on advantages and disadvateges of using daisy-chaining priority interrupt and polling for managing priority interrupt. 

3. Consider the following diagram showing transfer of data among CPU, Main Memory and Cache.

Main memory

 

a. Discuss with a suitable diagram how data can be transferred between main memory and cache memory given in diagram above, when using following methods:
i. Direct mappping  
ii. Set-Associative mapping  
b. Discuss in detail the performance obtained when CPU performs total of 3,450,000 memory references. 1,200,000 of which are miss in cache and 900,000 of which are hit in main memory.   

 

Rules & Regulations:

  • All resources should be cited using CU Harvard style.
  • The final assignment must have a Title page, Table of Contents, References/bibliography using CU Harvard Style and page numbers.
  • Title Page must have Assignment Name, Module name, Session, your name, ID, and the name of the faculty.
  • Softcopy in word format is to be submitted through Turnitin link on Moodle.
  • Viva will be conducted after the assignment submission as per the dates informed earlier.
     

Guidelines:
Assignment must be computer typed.

  • Font - Times New Roman
  • Font – Style - Regular
  • Font - Size - 12
  • Heading should be with Font Size 14, Bold, Capital and Underline.
  • Explain with suitable diagrams wherever required. Diagrams must be drawn using suitable software or by pencil.
  • Each student has to do the assignment individually / Students have to do the assignment collaboratively and each student should write a brief reflection on their contribution and learnings from group work.
  • You can refer books in e Library or use internet resource. But you should not cut and paste material from internet nor provide photocopied material from books. The assignment answers should be in your own words after understanding the matter from the above resources.

 

Important Policies to be followed
1. Student Academic Integrity Policy*:

MEC upholds the spirit of academic integrity in all forms of academic work and any form of violation of academic integrity shall invite severe penalty. Any benefit obtained by indulging in the act of violation of academic integrity shall be cancelled.
All cases of violation of academic integrity on the part of the student shall fall under any of the below mentioned categories:
1. Plagiarism
2. Malpractice
3. Ghost Writing
4. Collusion

5. Other cases

If the student fails a module and has a proven case of academic integrity violation in this module, the student is required to re-register the module. This is applicable to first and second offenders of plagiarism.

 

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