Computer Architecture & RISC (Reduced Instruction Set Computer) - Complex Instruction Set Computer) - IT Assignment Help

Assignment Task

QUESTION 1

During the concept phase and definition of next-generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performance. It is not enough to adopt a CPI-centric view alone in early-stage definition studies. One of the fundamental issues confronting the architect at this stage is the choice of pipeline depth and target frequency. Pipelining has emerged as a powerful technique for obtaining a high throughput rate. Performance of instruction pipeline suffers when conditional branch instructions are present in a program. 

(i) Discuss the basics of instruction pipeline and identify an approach to minimize a pipeline stall using relevant examples. 

(ii) The main idea is to understand the working of a pipeline in a processor. Discuss the various hazards that cause pipeline degradation and solutions to minimize them. 

QUESTION 2

In the ever-growing world of computer architecture, Instruction Set Architecture (ISA) is one of the major components of a computer system, as it provides the information about the instructions present in the system prior to the programmer. Having various implementations and uses, it is classified into various categories, RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer). These architectures differ substantially in terms of their underlying platforms and hardware architectures. The research topic on CISC and RISC has been a well-known research area for many years. Since modern processors have to address both power consumption and performance, it is important to compare these architectures to support future project decisions. 

(i) Describe the characteristics of each of these technologies and also include basic details regarding the various addressing modes, instruction formats along with the instruction execution cycle giving detailed information about RISC and CISC processors simultaneously.

(ii) Describe the major differences between a CISC instruction set and a RISC instruction set and discuss some key advantages and disadvantages of RISC as compared to CISC.

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