Computer Communications Laboratory Assignment

Assignment Task

1. Introduction

This handout describes the final project for ECE 429. The objective of this project is to understand a 32-bit Pipelined Central Processing Unit (CPU). As the name of the design declares, the word length of the data used in the circuits is 32 bits. Furthermore, since this circuit is pipelined, more than one instruction can be executed simultaneously. The operation of the circuit is synchronized by an externally set clock signal. Also the instruction signals for addressing the memory file, selecting the Arithmetic Logic Unit (ALU) operands and specifying the operation of the ALU are also external. The correct synchronization of those signals with the critical data path delay of the circuit that will determine the minimum operating period is one of the objectives of the project.

2. Circuit Description

An overview of the primary building blocks and signals of the CPU is shown in Fig. 1. As shown in Fig. 1, the primary building blocks are the memory file and the ALU. The external clock signal synchronizes the capture and release of data within the memory file block. The circuit is pipelined and each instruction is explained in two clock cycles. In the first clock cycle, the two decoders are used to decode the external address selection signals used for specifying the contents of the memory file that should be read at the memory ports in each clock cycle. Additionally, multiplexer blocks are used to select the operands for the ALU. In the next clock cycle, the ALU executes the specified operation. The ALU results can be read from the outside of the CPU through a tri-state buffer, based upon the value of the externally specified OEN (output enable) signal.

3. Memory File

The memory file of this design stores 32 32-bit words. There are two read ports in the memory file and one write port. The words to be read in each clock cycle are specified by the external 5-bit words address A and Address B. The internal configuration of the memory file is illustrated below in Fig. 2. As illustrated in Fig. 2, the primary storing element within the memory file is a D-register. The output of each D-register is connected to the two output ports of the memory file through tri-state buffers. The tri-state buffers are enabled by the decoded address (signals A and B) and the contents of the D-registers appear at the output ports A and B respectively. Furthermore, the value of address B specifies the word address in the memory file where the results of the ALU computation are stored in the second cycle of instruction execution. The writing of the ALU results within the memory file is synchronized by the clock signal.

4. Arithmetic Logic Unit (ALU)

The ALU of the circuit has two operands A and B and an implement the following eight functions:

- A * B : multiplication

- A + B : addition - A - B : subtraction

- B - A : subtraction

- A or B : logic OR function

- A and B : logic AND function

- A xor B : logic XOR function

- A xnor B : logic XNOR function

As illustrated in Fig. 1 the operand of the CPU can be selected among the following: - Operand A: Operand A can be selected between the read port A of the memory file and the externally defined data in. The selection is done by the external signal ASEL. - Operand B: Operand B can be selected between the read port B of the memory file and the logic zero value. The selection is done by the external signal BSEL.

5. Synchronization

To better understand the circuit synchronization sequence described below, please refer to Fig 1. The operation of the CPU is synchronized by the external clock signal. An instruction to be executed by the CPU is determined by the external control signals. An example of an instruction word is illustrated in Fig. 4. After the clock switches high the instruction is applied (fetched) to the signals that control the CPU operation. Since each instruction is executed in two steps, some of these control signals need to be stored at the internal registers of the CPU. On the first step of the instruction, these signals will specify the contents of the memory file that will be read from the read ports A and B. Also they will specify the operands of the ALU. In the second cycle of the operation the control signals will determine the operation to be executed internally the ALU, and the value of the ALU output.

The results of the ALU will be available of the circuit if the OEN signal is set, and it will also be written back in the memory file. The address in memory where the ALU result is written is specified.

6. RTL Simulation

We must ensure that there is no bug in the design before synthesis. We verify the correctness by running testing testbench. The whole cpu design in Verilog is provided, “cpu_xxx.v”, and a testbench for verifying the CPU, “tb_cpu.v”, where we test functionality for store, read, addition, and subtraction.

6.1. Place & Route and Post-P&R

Simulation Now, we are ready to run place and route using Cadence SOC Encounter. It wil take some time for the tool to finish the automatic layout generation. Once finished, you should check the final timing report in timing.rep.5.final in order to verify if all the circuit timings are met. Moreover, you will obtain the circuit netlist in final.v, which contains necessary buffers and inverters to overcome the interconnect delays in the signal propagation network and the clock distribution network. You should simulate it with the Verilog models of the standard cells, i.e. osu05_stdcells.v, and compare the result with the RTL simulation and the post-synthesis simulation. The command is:

7. Introduction: Case Study

Comparator Design in the ALU for the 32-bit CPU In this project, we will add a 32-bit comparator block into the ALU design. The function of a 32-bit comparator in Verilog is shown in Table 1. Suppose we have two 32-bit inputs (we assume them to be unsigned in this project) A and B. Since the result of comparing them can be A > B , A = B and A < B>

7.1 The structure of 4-bit comparator

The structure of 4-bit comparator is shown in Fig. 10. It is designed in a tree structure. At the bottom level (Level 2), there are 4 one bit comparators. Each of them is used to compare the corresponding bit in A and B. The meaning of the output f1 and f0 are the same as the meaning in Fig. 10 (f1f0=10 means a=b, f1f0=00 means a

b). Notice that the final comparison result depends on the comparison result of the most significant bit which has determined the relation of the two integers. Take the 4 bit comparator shown in Fig. 10 for example. If the results from MSB A[3] and B[3] has shown that A[3] > B[3] or A[3] < B xss=removed> B or A < B xss=removed xss=removed xss=removed xss=removed>

7.2 The structure view of the 32-bit comparator

The structure of the 32-bit comparator is shown in Fig. 11. You are supposed to finish the Verilog coding of this structure and include it in the ALU design. There should be three modules in your Verilog code: one_bit_comp, mux_4to2, and tree_comp. The definition part of each module is included in file cpu_comp.v, and they are listed in Fig. 12. You should finish the code in order to complete your new cpu design.

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