Design a Circuit for 1-Bit Full Adder With Proper Sizing, LVS and DRC - Engineering Assignment Help

Assignment Task

Description:  

In this project, you will form a team of 2 or work by yourself and build a 9-bit square-root carry-select  adder. Grading will based on area, speed and power. Use Cadence suite as done in Assignment to  perform all the tasks below. Each member must contirbute.  

Phase 1: (50%)  

1. Design a circuit for a 1-bit full adder with proper sizing. You want to read phase 2 requirements  also so to reuse this circuit as much as possible in phase 2. However, usually, less modification in  phase 2 means lower over performance in phase 1 because carry select adder only out-perform  regular adder when the bit number is larger (refer to teaching slides).  

2. Perform simulation to show it functions properly as a full adder. Need to cover all cases. You can  use transient simulation with appropriate pulses.  

3. Layout the circuit and perform LVS and DRC to make sure there is no violation.  4. Perform QRC to extract delay (use this to report delay)  

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