Design a State Machine that Operates From its Reset State - Engineering Assignment Help

Assignment Task

Q1.

Design a state machine that operates from its reset state as follows:
There is a single input called data.
Output A is low until it receives the sequence "1010" at which time it goes high for 1 clock cycle.
Output B is low until it receives the sequence Y at which time it goes high for 1 clock cycles.
The sequences may overlap.
This is to be a single state machine.
A and B should be free of false outputs.
Choose the STD notation as appropriate for the style of SM adopted (Mealy or Moore)
You are only required to provide a state transition diagram for the SM designed.
Y is based upon the last digit in your student ID as follows:
0,4,8 => "1100" 1,5,9 => "1110" 2,6 => "1101" 3,7 => "1111"
e.g. for ID = 123458X => Y (for 8) = "1100".

3532939295347Your ID# 1234567
Y = NNNN
00Your ID# 1234567
Y = NNNN
Paste or draw state diagram HERE - this may be a legible scan or photo of a hand-draw figure.

Q2.

Design a VHDL module as shown below. It accepts a 4-bit unsigned number and determines if it is evenly divisible by each of 2, 3, 4, 5, 6 and 7. This is indicated by separate outputs for each value.

Notes:

· The input is a single port (std_logic_vector)

· The outputs are multiple individual ports (std_logic) as shown in the block diagram.

· Mathematic operations (division etc) are NOT permitted in the VHDL (for efficiency reasons).

· Hint: It may be useful to know that aggregates may appear on the left of an assignment.

· Simplicity and clarity of approach will be considered in marking e.g. Boolean equations would not be a good approach (about 1/5 I’d say).

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