Design And Construction Digital Calendar And Clock Assignment

Assignment Task

You need to implement a digital calendar and clock with the following functionalities:

• Initially, the calendar and clock should start from a specific date (e.g., 30.07.2024 18:30:00).
• Hours and minutes should be displayed on a 7-segment display in a 24-hour format.
• Seconds should be shown in binary on LEDs.
• Two buttons should allow adjusting the hours (increase and decrease).
• Two buttons should allow adjusting the minutes (increase and decrease).
• Switches should be used to adjust the seconds (each switch corresponds to one LED).
• One button should pause and resume the clock (this is necessary for adjustment; the clock can be resumed after making adjustments).
• One switch should be used to speed up or slow down the clock (based on FPGA frequency or slightly slower, depending on your choice) to quickly observe date changes.
• One switch should perform a reset function, returning the system to its initial state (e.g., starting again from 30.07.2024 18:30:00, adjusting the LEDs, 7-segment display, etc., accordingly).
• For the calendar, you need to use the UART protocol. The user should be able to view the current date and time in a format like 30.07.2024 21:47:54 on the terminal screen after typing a special character or word from the keyboard of a computer connected to the FPGA and pressing Enter.
• Similarly, if the user wants to set the date and time via UART and enters a character along with (additional start-end character or word, or based on character count), for example, K15082024153008, the date and time should be set to 15.08.2024 15:30:08 and continue from there. The 7-segment display and LEDs should be adjusted accordingly.
• You can determine the UART baud rate as you wish

`timescale 1ns / 1ps

module clock (

input clk,

input rst,

input hour_inc,

input hour_dec,

input min_inc,

input min_dec,

input [11:0] year_set,

input [3:0] month_set,

input [4:0] day_set,

input [4:0] hour_set,

input [5:0] min_set,

input [5:0] sec_set,

input pause,

input accelerate, //!!! ADD THIS !!!///

output reg [11:0] year, 

output reg [3:0] month,

output reg [4:0] day,

output reg [4:0] hour,

output reg [5:0] min,

output reg [5:0] sec

);

wire clk_slow;

clock_divider clk_div ( //!!! I ALSO CHANGED THE CLOCK DIVIDER !!!///

.clk(clk),

.rst(rst),

.DIVIDE_BY((10*8)/2 - accelerate(10**8)/4),//!!! ADD THIS !!!///

.clk_out(clk_slow)

);

reg [11:0] year_n;

reg [3:0] month_n;

reg [4:0] day_n;

reg [4:0] hour_n;

reg [5:0] min_n;

reg [5:0] sec_n;

reg run = 1;

reg run_n;

reg [5:0] days_in_month;

reg [5:0] prev_set_sec;

reg [5:0] prev_set_sec_n;

always @* begin

year_n = year;

month_n = month;

day_n = day;

hour_n = hour;

min_n = min;

sec_n = sec;

prev_set_sec_n = prev_set_sec;

case (month)

'd1, 'd3, 'd5, 'd7, 'd8, 'd10, 'd12: days_in_month = 'd31;

'd4, 'd6, 'd9, 'd11: days_in_month = 'd30;

'd2: days_in_month = (year % 'd4 == 0) ? 'd29 : 'd28;

default: days_in_month = 30;

endcase

run_n = pause ? ~run : run;

if (run_n) begin

sec_n = sec + 1;

if (sec_n >= 'd60) begin

sec_n = 0;

min_n = min + 1;

if (min_n >= 'd60) begin

min_n = 0;

hour_n = hour + 1;

if (hour_n >= 'd24) begin

hour_n = 0;

day_n = day + 1;

if (day_n > days_in_month) begin

day_n = 1;

month_n = month + 1;

if (month_n > 'd12) begin

month_n = 1;

year_n = year + 1;

end

end

end

end

end

end else begin

if (hour_inc) begin

if (hour == 'd23) begin

hour_n = 0;

day_n = day + 1;

if (day_n > days_in_month) begin

day_n = 1;

month_n = month + 1;

if (month_n > 'd12) begin

month_n = 1;

year_n = year + 1;

end

end

end else begin

hour_n = hour + 1;

end

end else if (hour_dec) begin

if (hour == 0) begin

hour_n = 'd23;

day_n = day - 1;

if (day_n == 0) begin

month_n = month - 1;

if (month_n == 0) begin

month_n = 'd12;

year_n = year - 1;

end

case (month_n)

'd1, 'd3, 'd5, 'd7, 'd8, 'd10, 'd12: days_in_month = 'd31;

'd4, 'd6, 'd9, 'd11: days_in_month = 'd30;

'd2: days_in_month = (year_n % 'd4 == 0) ? 'd29 : 'd28;

default: days_in_month = 30;

endcase

day_n = days_in_month;

end

end else begin

hour_n = hour - 1;

end

end

if (min_inc) begin

if (min == 'd59) begin

min_n = 0;

hour_n = hour + 1;

if (hour_n >= 'd24) begin

hour_n = 0;

day_n = day + 1;

if (day_n > days_in_month) begin

day_n = 1;

month_n = month + 1;

if (month_n > 'd12) begin

month_n = 1;

year_n = year + 1;

end

end

end

end else begin

min_n = min + 1;

end

end else if (min_dec) begin

if (min == 0) begin

min_n = 'd59;

hour_n = hour - 1;

if (hour_n < 0>

hour_n = 'd23;

day_n = day - 1;

if (day_n == 0) begin

month_n = month - 1;

if (month_n == 0) begin

month_n = 'd12;

year_n = year - 1;

end

case (month_n)

'd1, 'd3, 'd5, 'd7, 'd8, 'd10, 'd12: days_in_month = 'd31;

'd4, 'd6, 'd9, 'd11: days_in_month = 'd30;

'd2: days_in_month = (year_n % 'd4 == 0) ? 'd29 : 'd28;

default: days_in_month = 'd30;

endcase

day_n = days_in_month;

end

end

end else begin

min_n = min - 1;

end

end

if (sec_set != prev_set_sec) begin

sec_n = sec_set;

prev_set_sec_n = sec_set;

end

end

end

always @(posedge clk_slow) begin

if (rst) begin

year <= 'd2024;

month <= 'd6;

day <= 'd30;

hour <= 'd23;

min <= 'd00;

sec <= 'd00;

run <= 'd1;

prev_set_sec <= 0;

end else begin

year <= year_n;

month <= month_n;

day <= day_n;

hour <= hour_n;

min <= min_n;

sec <= sec_n;

run <= run_n;

prev_set_sec <= prev_set_sec_n;

end

end

endmodule

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