Develop an Instruction Set Simulator (ISS) - RV321 Subset - Computer Science Assessment Answer

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Computer Science Assessment Answer

TASK: Your task for this assignment is to develop an instruction set simulator (ISS) for the RV32I subset of the RISC-V instruction set. An instruction set simulator is a program used by computer architects to simulate execution of a computer’s instructions. It contains representations of the computer’s memory and the internal registers of the CPU. It responds to commands that specify initialization and inspection of the memories and registers, and control execution of instructions. The RISC-V instruction set is described in The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA, available on the course web site. The RV32I subset is described in Chapter 2 of the Instruction Set Manual. The instruction encoding is summarized in Chapter 25. For this assignment, you should implement just the RV32I base integer instruction set, with the following exceptions: • FENCE: These instructions should be decoded as legal instructions, but perform no operation. • ECALL, EBREAK: These instructions should be decoded as legal instructions, but a message should be displayed indicating they are unimplemented. For load and store intructions, you can assume that the effective address is properly aligned. For any fetched instruction word that does not represent an RV32I instruction, a message should be displayed indicating the instruction is illegal. In Stage 2, you will implement exception handling, which will be used for illegal instructions. I have provided a skeleton program on the course web site for you to use as a starting point. The program is written in C++ and is located in the Assignment file folder (also linked in the Assignment module). You can download either rv32sim.zip or rv32sim.tgz; the content is the same in each. The skeleton program implements processing of command-line options and input commands. Your task is to implement classes to model the processor and memory. Header files are provided showing the member functions required. You can add additional classes if you need to. The only command-line option you need to implement at this stage is the -v option to enable verbose output. Further options may be implemented in Stage 2. If the -v option is specified on the command line, your program can display debugging information. If the option is omitted, your program should display only the output required for each com- mand. Your program must format that output exactly as specified below, since the assessment process will compare you output with expected output. The rv324sim program reads commands from the standard input stream, one command per line. The commands are:

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