ECTE433 - Embedded Systems - Engineering Assignment Help

Assignment Task

Project Task 1: Integer Divider
Division is an essential but difficult operation in embedded systems. In integer division, the relationship between the inputs (numerator and denominator) and the outputs (quotient Q and remainder R).
The numerator is also known as dividend, and the denominator is also known as divisor. For background information on integer division. This project requires you to develop a high-speed FPGA design for integer division.
• The device has three input signals: ‘N’, ‘D’, and ‘start’.
• Signals ‘N’ and ‘D’ are unsigned integers. The bit-width of ‘N’ and ‘D’ is W bits, where W is a parameter specified in the PreLoadFcn function of the Simulink MDL file. W can be set to 8, 10, 20, 32 and so on.
• Signal ‘start’ is a Boolean variable. When signal ‘start’ goes HIGH, calculation should begin. It is assumed that signal ‘start’ will not go HIGH again until calculation is completed.
• The device has four output signals: ‘Q’, ‘R’, ‘valid’, and ‘clock_count’.
• Signal ‘Q’ is the quotient, and signal ‘R’ is the remainder. They both have a bit-width of W.
• When the device finishes calculating ‘Q’ and ‘R’, it should make the Boolean signal ‘valid’ go HIGH for exactly one clock cycle.
• Output signal ‘clock_count’ should store the actual number of clock cycles used for calculating ‘Q’ and ‘R’. For example, if calculation starts at clock cycle 2 (‘start’ = HIGH), and finishes at clock cycle 20 (‘valid’ = HIGH), then ‘clock_count’ = 20 − 2 = 18.
• The design must be created using MATLAB Simulink and Xilinx System Generator. The following built-in Xilinx blocks must not be used: Divider Generator, Divide, Black Box, MCode, Mult, CMult, Natural Logarithm, Reciprocal, and Square Root.
• Xilinx ISE version 14.4, MATLAB 2012b, Windows 7 or 10 64-bit are the assumed platform.

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