EE318: Computer Architecture and Design Cache Simulator Programming Assignment - Engineering Assignment Help

Assignment Task:

TASK:

Section I: Introduction In this assignment, you are required to implement a single level cache simulator and analyze the performance of various cache architectures using real-world program traces. For this purpose, you will write programs (C/C++/Python) to read in the given memory traces and simulate different cache architectures and determine the performance and overheads. Information about the traces are given in Section II.

The cache architectures you required to implement are listed in Section

III. Some of the architectures are mandatory to implement for all students. The results to be reported are given in Section IV. Apart from this, students have the liberty to explore research papers to implement cache architectures and replacement algorithms to take the performance as close to an ideal cache as possible i.e. 100% hit-rate. A leaderboard will be created and shared to keep track of the best algorithm that the class has designed and implemented. This is described in Section

V. This is optional. Section VI describes the submission procedure. Section II: About the Traces The traces you have been given are generated from runs of a subset of programs from the MiBench embedded benchmark suite (http://vhosts.eecs.umich.edu/mibench/). The link also contains a characterization reference paper which you can peruse for sanity checks for your cache simulator. They contain the complete instruction and data memory access trace of the programs. Each line of the trace file has only one field – the memory address accessed in 64-bit HEX format. Below are the first four lines of a trace file: 0x00007FFFD9C0EDB0 0x00007FFFD9C0EC98 0x00007FFFD9C0ECAC 0x00007FFFD9C0ECB0 You can also generate traces of the remaining benchmarks and see how they perform for each cache architecture. Section III: The Cache Simulator Any cache architecture has 5 primary configuration parameters

i) CSIZE: Cache Size (data alone)

ii) BSIZE: Block Size,

iii) ASSOC: Associativity,

iv) RPOL: Replacement policy (for associative caches),

v) WPOL: Write policy Your cache simulator should accept the parameters listed above and determine the required performance metrics by simulating each line of the trace file sequentially. For this, you will have to maintain a data structure for the cache and manipulate it according to each memory access. Simulate each of the following architecture configurations and report the performance metrics in the required formats as given at the end of this section. 1) CSIZE: vary from 256 bytes to 4MB in convenient strides 2) BSIZE: vary from 4 bytes to 512 bytes

3) ASSOC: Direct Mapped, 2-way, 4-way, 8-way, 16-way 4) RPOL: LRU, NFU, CLOCK, RANDOM (only for set-associative caches)

5) WPOL: Write Through, Write Allocate *PLEASE NOTE THAT COME OF THE CONFIGURATIONS ARE NOT PRACTICALLY POSSIBLE e.g. BSIZE > CSIZE, or (Num. of Ways * Num. of Sets * BSIZE) > CSIZE. Prune these configurations out before simulating.

Section IV: Performance Metrics to be reported

1. For each cache configuration and benchmark combination (and all benchmarks cumulatively):

a) Given ASSOC and CSIZE, vary BSIZE and plot miss-rate (Total, Cold, Conflict, Capacity). Do the same for different combinations of ASSOC and CSIZE

b) Given ASSOC and BSIZE, vary CSIZE and plot miss-rate (Total, Cold, Conflict, Capacity). Do the same for different combinations of ASSOC and BSIZE

c) Given CSIZE and BSIZE, vary ASSOC and plot miss-rate (Total, Cold, Conflict, Capacity). Do the same for different combinations of BSIZE and CSIZE You can also plot a 3D graph varying all 3 parameters.

2. Also, plot the Storage Overhead for each cache architecture (does not vary with benchmark).

3. The best cache architecture for each of the given benchmark memory traces.

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