EE4015: Structures for Discrete-Time Systems - Digital Signal Processing - Engineering Assignment Help

Assignment Task:

Content

Frequency Response Analysis
• Frequency Response Estimation
• Magnitude and Phase Responses
• Frequency Response of FIR Systems
• All-Pass Filters
• Second Order Resonant Filter
• Notch Filter Design using Pole-Zero Placement

Structures for Discrete-Time Systems

• Block Diagram Representation
• Signal Flow Graph Representation
• Non-Recursive Structures for FIR System
§ Direct Form and Cascade From
• Recursive Structures for IIR System
§ Direct Form, Canonic Form, Cascade Form and Parallel Form

• Comparison of Different Structures

Implementation of Difference Equations

• The implementation of difference equations requires delayed values of the
§ input
§ output
§ intermediate results
• Computing y[n] involves y[n-1], y[n-2], ..., y[n-N], and x[n], x[n-1],...,x[n-M]. That is, we need
§ Delay elements or storage
§ Multipliers
§ Adders (subtraction is considered as addition)

Complexity of the Discrete-Time Systems
How many storage elements are needed?
How many multipliers are needed?
How many adders are needed?
• Computations of y[n] can be arranged in different ways to give the same difference equation, which leads to different structures for realization of discrete-time LTI systems
• 4 basic forms of implementations : Direct Form, Canonic Form, Cascade Form and Parallel Form
• An implementation can be represented using either a Block Diagram or a Signal Flow graph

Features of these Basic Operations
• Although an adder can generally deal with more than two sequences, here we consider two signals in order to align with practical implementation in
microprocessors.

• When a > 1 , it corresponds to signal amplification while the signal is attenuated for a < 1 . Note that a multiplier usually has the highest implementation or computational cost and thus it is desired to reduce the number of multipliers in different systems.

• The transfer function Z%' corresponds to a unit delay. It can be implemented by providing a storage register for each unit delay in digital implementation. If the required number of samples of delay is D > 1 , then the corresponding system function is z!".

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