EE577A - VLSI System Design Assignment

Assignment Task

i. SRAM Array Design

Figure 1 provides a 512-bit SRAM with four 128-bit banks. You need to understand the structure and design its schematic. The word length is 16 bits. You need to minimize the area×delay product. The delay of the SRAM array is the read delay or the write delay, whichever is higher.

a) We assume both the address bits (A[4]-A[0]) and their complement (A_bar[4]-A_bar[0]) are given.

b) Size you SRAM bit-cell such that the Read SNM is at least 200 mV and Write SNM is at least 395 mV.

c) Use one sense amplifier for each column after multiplexed lines. Note that when you are doing the simulation for a single cell, using only one word line and one column, you should include some dummy lumped capacitance to mimic the parasitic effects caused by the rest of the word lines and columns, 1-output line from Row decoder, read and write column mux (Refer to TA Discussion Sessions for more information of this).

d) Design the row decoder. The output of the row decoder should be a pulse of appropriate width, i.e., you must use a properly delayed voltage signal to turn off the row decoder (you can use decoder_en signal from your vector file as input) after the bit line has discharged to VDD - ∆V, (∆V = 80-100mV) to start pre-charging the bit lines for the next clock cycle. Also, consider using pre-decoders to reduce the area occupied by wires. Optimize the decoder for minimum delay. Use logical effort to model the delay of the decoder and justify your decoder design. For example, you can justify the design by comparing it to two other functionally equivalent implementations, show the logical effort calculation for all three implementations, and argue why you picked your implementation. You can use the load capacitance estimated in part c as an estimate for decoder output load.

e) Use pMOS pass transistors to design the column read mux and nMOS pass transistors to design the column write mux. Data is stored in interleaved manner across the 4-banks. Each bank stores only the 4-bits of a given word and across the 4-banks you will get the 16 bits of the word after multiplexing.

f) Output register: latch the output of the SRAM into a 16-bit register. You can use your register from previous labs. Other control signals can be added for the 16-bit register, if necessary, for example, the set/reset.

ii. Specifications

a) You could generate other control signals for the SRAM array, if necessary, for example, the pre-charge signal and the decoder enable signal. You can specify these additional control signals in your stimulus file manually to make the whole design work.

b) VDD = 1.0 V.

c) All data clock transitions are 5 ps.

d) The clock signal has 50% duty ratio and infinite driving ability.

e) Your design should fulfill the following specifications in terms of delay.

• Pre-charge is considered complete when the bit lines reach 0.95VDD.
• Decoder delay is the delay from rising edge (VDD/2) of clock to the rising edge of the WL (VDD/2). Inputs to the decoder are applied through flip-flops, you can design your own flip-flops or use one from the PDK library.
• Bit-line delay is the delay from Rising edge of WL (VDD/2) to the rising edge of sense_en signal (VDD/2).
• Sense amplifier delay is the time from rising (VDD/2) of sense_en signal to the falling of OUT or OUT %%%%%% to (VDD/2) (size M0, M1, and M2)
• Note that sense_en signal is activated only after the BL and BLB has developed a voltage difference of 80-100mV.
• Register delay is the time from falling of OUT or % OUT %%%%% to (VDD/2) of the sense amplifier to the rising edge of the output register to (VDD/2).
• The total read delay is the delay from rising edge of clock to the rising edge of output register.
• Remember that write delay should be equal to or less than read delay.

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