EEL 5741- Advanced Microprocessor Systems - Memory Hierarchy Performance Analysis - Systems Analysis Assignment Help

Assignment Task:

Introduction
In this project, we will use SimpleScalar simulation tools to study the memory hierarchy performance with memory hierarchy organization. There are three tools in SimpleScalar that can be used for this purpose: sim-cache, sim-cheetah, and sim-outorder. Sim-cache and sim-cheetach are for the in-order execution, while sim-outorder is for the out-of-order simulation. In this project, we use sim-cache as it is good enough for this project.

What to do:

1. Compile the matrix multiplication program matmul.c into an executable using gcc and test it using simple examples to make sure the program works correctly. Then
remove the output section in your program and recompile it (without using any optimization option) use SimpleScalar compiler.
2. Cache Analysis Assume 50 by 50 matrices for following simulations. If the cache specifications are not given, use the default values set in the SimpleScalar.
a. Cache/block size Simulate matmul.c with different data cache and block size. Assume a directed mapped cache. Change the cache sizes as 2K, 4K,
8K, 16K, 32K, 64K each with different block sizes: 16, 32, 64, 128, 256. Compare and plot the data cache miss rates. (Note: when you set the block size, the block size for the first level must be no larger than that for the lower level.)
b. Cache associativity Simulate matmul.c with different set associativities. Assume one level data cache with 8K size. Change the degrees of data cache to be 1, 2, 4, 8, 16. Compare and plot the data cache miss rates
c. Unified v.s. Split cache Simulate matmul.c with both unified and split cache. Assume one level and 2-way set associative cache with total sizes of 4k, 8k,16k, 32k, 64k, 128k and block size of 32. Compare and plot the cache miss rates for instruction and data memory access.
d. Block replacement policy Simulate matmul.c with three different block replacement policies. Assume one level data cache with total cache sizes as 4Kand 32K, each of which has degree of set associativity as 1, 4, and 32. Compare and plot the data cache miss rates.
e. Multilevel Cache Simulate the execution of matmul.c with two levels of data cache. Let the first level cache to be 8K direct mapped cache, the
second level be 2 way set associative caches with sizes as 8k,16k, 32k, 64k,128k. Compare and plot the local as well as the global miss rate for the second level data cache.
f. Three types of cache misses Simulate the execution of matmul.c with one level of data cache with sizes as 8k,16k, 32k, 64k, 128k and associativity 1,
2, 4, 8. Compare and plot the cache miss rate for the capacity and conflict cache misses.
g. TLB Simulate matmul.c with two levels of data cache. Let the first level cache be 1K direct mapped cache, the second level be 2-way set associative caches with size of 32k. Set data TLB to be directed, 2-way, and fully associative with 4 and 8 entries (Let the page size be 1K). Compare and plot the data TLB misses. Approximately how many pages needs to be accessed for the data?

What to hand in - 
Use tables and figures (using MS Excel for example) to present your experimental results and attach your discussion of these results in ONE pdf file. Again, a summary section is mandatory for all the students to summarize the conclusions and/or any thoughts, experience you get from the projects.

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