ELEC4720 - Programmable Logic Design - Structural System Verilog - MIPS Processor - Multiple Divide Circuit - Engineering Assignment Help

Assignment Task:

ELEC4720 Programmable Logic Design Engineering Assignment Help

Assignment 1

Problems

1. Design a structural System Verilog module for a 7 segment display decoder with a four-bit input C, and a seven-bit output Y, which can be used to display the characteristics associated with the hexadecimal code represented by C on a 7-segment display on the development board. Instantiate your seven-segment decoder module on the development board, and connect it with the switches and the seven segment displays to verify its functionality. To design the structural module you are required to carry out Boolean simplification, e.g., by using Karnaugh maps.

2. Write a system Verilog module to multiply two 4 bit wide numbers to produce a 7-bit wide result of the multiplication. Create a test circuit on the development board to demonstrate the multiplier module is working properly.

3. Write that system Verilog module to multiply two 8 bit wide numbers to produce the 15-bit wide result of the multiplication. Design an appropriate testbench to test your multiplier module, and run the testbench in Modelsim to verify that the multiplier module produces correct results.

4. In this assignment, you will design the ‘logic unit’ of the MIPS processor. This unit has one control unit F and two data inputs A and B. F is 2 bit wide. Each of A and B are 2n bit wide, where n is an integer. Typically n > 2, but that is not important for this assignment. The output Y is also 2n bit wide.

(a) Design an appropriate parameterized (n is the flexible parameter) system Verilog module to implement the logic unit.

(b) Design an appropriate top-level module to test the circuit on the development board.

5. Use the ‘+’ operator in System Verilog to implement a parameterized 2n bit adder so that we can freely vary n during instantiation. Next you will use the above adder module to build a circuit that will either add or subtract depending on a control input s. Apart from the control input this circuit has two data inputs A and B, and an output Y . Each of A, B, and Y are 2n bit wide. The functional specification of this circuit is given in Table 5 . You are required to provide a System Verilog implementation of a circuit implementing the specification by using the adder (mentioned above) and a 2:1 multiplexer. Your design should not use more than one adders. This should be a parameterized module that allows us to choose n during instantiation.

6. In this assignment, you will design the top-level instruction classifier, which is central to the instruction decoder in a MIPS processor. A MIPS instruction has a 6 bit “Opcode” input which determines what it is supposed to do. This module has 7 single-bit outputs R, B1, J, B2, I, F, M. Table 3, which is an extract from the MIPS instruction set gives a summary of MIPS opcodes.

7. In this assignment, you will design a shifter unit which can be used readily in a MIPS processor. In particular, we focus on the shift instructions among MIPS R-type instructions. Each machine instruction in a MIPS processor has like a 6-bit field called “Funct”

(a) Design a MIPS compatible shifter that has three inputs. The first input A is shifted by an amount given by the other data input Sh. The third input F1:0 is the control input. This control input determines the relation between the input operands A and Sh, and the output Y as per Table 4. Note that if Sh is n bits wide then A and Y are 2n bits wide. You can take n = 4 in this assignment. However, with very little extra effort you can produce a parameterized module that can handle any n.

(b) Now you will use the module designed in the previous part to design hardware that readily supports MIPS R-type shift instructions. The there data inputs to this hardware are denoted as b, a and c. For a 2n bit processor b, a and the output y are 2n bit wide. On the other hand, c is n bit wide. The relation between the inputs and the output is controlled by the control input F2:0 as tabulated in Table 5, where it is assumed that n = 4.

(c) Design an appropriate main module to test the circuit on development board.

8. In this assignment, you will design multiply-divide hardware which can be used readily in a MIPS processor. In particular, we focus on the MIPS R-type instructions. Each machine instruction in a MIPS processor has a 6-bit field called “Funct” (denoted briefly by F here).

9. In this assignment, you will design an arithmetic logic unit (ALU) which can be used readily in a MIPS processor. In particular, we focus on the arithmetic logic instructions among MIPS R-type instructions. Each machine instruction in a MIPS processor has a 6 bit field called “Funct” (denoted briefly by F here).

A MIPS compatible ALU takes F3:0 as a control input. This control input determines the relation between the data inputs A and B, and the output Y as per Table 7, which is a part of the set of MIPS R-type instructions.

A step by step design process is described in the lecture slides. Note that the ALU hardware includes an adder. For this assignment, you are free to choose any adder implementation including the behavioural one using System Verilog + operator.

• Design an n bit wide parameterized ALU module as per Table 7. The ALU should have two additional outputs Cout and OV to flag the carryout and arithmetic overflow in arithmetic operations.

• Create an appropriate top-level module to test the ALU circuit on the development board.

Assignment 2

This assignment consists of three steps:

2.1 First you will design the instruction set architecture of a microprocessor. You will also develop the logic circuit to implement your design.

2.2 Then you will implement your design on the DE2 board. At this stage, you will implement a single-cycle processor.

2.3 In the final stage you will design a pipelined processor which is about 5 times faster than the single-cycle design.

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