EN0720:Digital Design Automation – System Verilog - IT Assignment Help

Assignment Task:

Task:

Objectives:
• To create SystemVerilog (SV) design source descriptions for the various component parts of a Monitoring System comprising an Analogue-to-Digital Converter, Asynchronous Serial Data Transmitter and Receiver along with a display.
• To incorporate an IP (Intellectual Property) module into the design using customisation and interfacing.
• To perform simulations of individual design modules using SV test-modules and the Vivado® Simulator.

• To perform simulations of the complete Monitoring System top-level module using a SV test-module and the Vivado® Simulator.

• Synthesise and Implement the Monitoring System, targeting a Field Programmable Gate Array development board (Artix-7 FPGA on Digilent® Basys3® development board).

• Demonstrate the operation of the FPGA implementation of the Monitoring System using the Basys3® development board by means of a so-called ‘hardwired loop-back’ test.
 

Learning Outcomes:
See Assignment Specification document: ‘EN0720_KD7020_assignment_2020_21_Specification_part1.docx’. Software and Hardware Resources:
• Xilinx Vivado ® FPGA/CPLD Design Suite. Available in labs E204/206 and as a free

download (Vivado HLS WebPACK Edition) from: http://www.xilinx.com/products/design- tools/vivado/vivado-webpack.html

• Digilent® Incorporated ‘Basys3’ Artix-7 FPGA Development Board. Reference Manual. Supporting Documentation (available on eLearning portal)
• Powerpoint presentation on Register Transfer Level Design using the SystemVerilog hardware description language. See document on eLearning: ‘RTL with SystemVerilog 2016.pdf’.

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