Formal Finite State Machine Design Procedure - Engineering Assignment Help

Assignment Task :

Aims

To introduce the principle of design choice for a digital system and become aware of its impact on circuit design and implementation.

Learning Objectives (LO)

Students should be able to:

LO 1. appreciate the impact of design choice

LO 2. understand the benefits of a formal finite state machine design procedure

LO 3. appreciate the problems that non-formal design procedures cause

LO 4. use a commercial circuit simulator to verify a design.

LO 5. Implement a design in Verilog HDL

LO 6. Appreciate the benefits of HDLs

Part 1

• Implement the Lab introduction example solutions, see BBL.

• Open a new project, ideally use the MX7000 device but you must record which device you use. Remember, no spaces in directory path or project/filenames. H:drive is best as its backed up. However, you can you local memory sticks but back them up!

• Open a new design file, check it saves to <project name>. bdf

• Copy and paste the template solution available on BBL. Open up the template, select all and then copy and paste into <projectname>.bdf

• Complete the design, saving regularly. Use the boolean equations given in lectures. See BBL

• Compile and correct all compile errors. Note the warning messages, some are not important, but some are! Check you have disk space to compile your circuit, it generates large files!

• Open up a new waveform file. Set the end time and grid spacing, bring is all inputs, output, and registers (post fitted) into the waveform file.

• Ensure everything has sensible names, groups appropriately and displayed correctly!

• Save the file, it should save to <projectname>.wav automatically.

• Using appropriate input stimuli, simulate the design to verify it is /or is not working. If it is not working, identify the error and record the process you followed to correct them in your lab book (word document!). You might wish to use some of these examples in your final report.

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