Identification and Significance of the Problem or Opportunity, and Technical Approach

Assignment Task

In response to U.S. DOE SBIR topic 33e, “ High-Channel Count Electronic Tools for Picosecond (ps) Timing”, Alphacore will develop radiation-hard Phase Synchronization and Jitter Cleaning System (PSJC) for Clock Generation and Distribution. The significance of this innovation is that the system can adjust/control the phase at front-end modules at sub-pico second resolution using “delay-discriminator based feed-forward phase noise cancellation PLL” while consuming ultralow power, as needed in DOE front-end detector modules .

Timing information is an critical tool in background reduction techniques in HEP experiments. Future experiments will require 4D or 5D detectors capable of time resolution in the picosecond range. Typical circuit blocks for precision timing generation such as Phase-Locked Loops (PLL), Delay-Locked Loops (DLL), Timing Discriminators and Time to Digital Converters (TDCs) that operate with low power in extreme environments are needed as recognized in the DOE HEP report. To synchronize operation precision clock distribution strategies need to be investigated and optimized for precision timing SoCs.Distributing a clock signal from a central location to each detector/dish suffers from drifting phase dependencies. As a result, precision clock distribution techniques that actively monitor delays and maintain pico-second synchronization across the full array are critically needed. Alphacore has been discussing with relevant DOE HEP community members along with CERN HL-LHC collaboration members to gain more information about the requirements and development status for the requested technology. These meetings have been both physical (at TWEPP) and via teleconferences and phone calls. The discussions focused on details of the existing needs present at HL-LHC and also what the expected needs are for future experiments such as PUMA (packed ultra-wideband mapping array). Some of the key goals of DOE according to its report[1] titled “DOE Basic Research Needs Study on High Energy Physics Detector Research and Development “ are :

The following approaches should be taken by the U.S. HEP community to meet the goals for future experiments.

• As a first step, define the system requirements for the various use cases and then develop laboratory test stands for quantitative studies of synchronization techniques
• Follow with a multi-year task to demonstrate 25 ps synchronization across tens of meters distance scales under laboratory conditions
• Refine the technique above to achieve the goal of robust synchronization of 5 ps or better
• Achieve the ultimate goal of robust synchronization of 1 ps over 1 km in an outdoor environment for the PUMA experiment requirement”

Alphacore’s solution uses a two-way time-frequency method to achieve sub-ps synchronization while meeting the performance at high levels of radiation (tolerant to both TID and SEE effects). This technique coupled with our innovative “delay-discriminator based feed-forward phase noise cancellation PLL” will achieve phase synchronization of up to 200fs or better while consuming ultralow power. Alphacore’s PSJC system will be implemented in the TSMC 28nm CMOS process, and the goal is to meet the stringent TID requirements of the HL-LHC (and other DOE HEP experiments). The eventual goal is TID hardness up to gigarad levels. Alphacore has been following CERN’s TID test results for the proposed process and these results will be leveraged in this development. In addition to nineteen full-time CMOS mixed-signal design engineers, Alphacore currently employs three experienced PhD-level researchers, who specialize in radiation effects testing, modeling and hardening techniques , and who have published over 200 papers in this field, combined. Accordingly, the program will have significant portion devoted to the radiation effects analysis and mitigation techniques.

TSMC General Purpose (GP) 28nm CMOS technology. ⁴ Muse Semiconductor[2] has TSMC 28nm MPW runs available once a month, and the price is “reasonable”, namely $13k per every mm ² used. The return time is fast, just 3 months. Alphacore has successfully used Muse for 28nm CMOS technology tapeouts in another program. The availability of low-cost prototyping will allow the proposing team to fabricate several test chips in Phase II, which will mitigate the program risk

Alphacore has significant plans in commercializing the PSJC technology developed in this program. The technology will be operable in the extreme environments of large particle colliders, but it also will have pure performance metrics equal to or better than the top commercial synchronization technologies. This technology is particularly useful in laser range finders for several defense applications, 3-D LIDARs in autonomous vehicles.

Current Level of Technology

As per the DOE’s Basic Research Needs Study on High Energy Physics Detector Research and Development report, future high energy physics experiments in all frontier areas emphasize pushing towards the 1-picosecond timing range ¹ . “The future Energy Frontier experiments extreme pile-up and occupancy must be mitigated with high-granularity tracking detectors and calorimeters capable of precise measurements of particle time-of-arrival (ToA)” ¹ . Any system that relies on precisely measuring the time interval between signals from different detector channels of DOE HEP experiments requires a high quality, low-jitter and low-wander clock distribution system. To reach the 1 p s measurement level, the clock distribution system will need to be stable at the sub-picosecond level. Two-way time-frequency transfer methods have been reported to achieve sub-ps synchronization in a number of DOE laboratories, but cannot be fielded in practical systems, cost-effectively synchronizing thousands of clocks across kilometer scales and survive high dosage of radiation.

As per the prior research, collider detectors have traditionally derived timing references from the machine RF signals which in turn are synchronized to a master oscillator with exceptionally high stability. These derived clocks from the central machine timing are used to generate the detector timing and synchronization messages which are then distributed as needed to the front- and back-end electronics over optical fiber links. An example in this case if CERNs lpGBT [1] chip. While the lpGBT system is not intended for picosecond phase correction, several of its blocks such as eClock and phase shifters already have performance issues even in non-radiation environment (typical laboratory conditions) due to high jitter ⁵ and other blocks such as PLL have SEU issues under radiation. In next-generation colliders however, the timing precision required to disambiguate interactions will further go down to 25 ps in e+e- machines, and better than 5 ps in hadron colliders. For events that are registered on different detector elements, it follows that the difference in clock propagation delays must be matched (or measured) to similar precision. The adjustable delays, voltage controlled oscillators, jitter attenuators, and other on detector synchronization circuitry must be able to survive the radiation environment which is not a readily available solution .

 Also shown in prior work on particle accelerator experiments, the LHC Bunch Clock is one of the most critical measurement signals delivered to the experiment modules. It is generated from the 400MHz RF signal controlling the beams in the accelerator by an integer division of 10. The clock signal represents the frequency at which the bunches are crossing each other at each experiment, it is the master synchronization signal for all the event detection electronics systems. Its center frequency is approximately 40.079MHz, but based on energy, particle type, it varies with beam parameters by a few hundreds of Hz[2]. As noted in [[3]], both ATLAS and CMS projects are planning to utilize novel detectors with accuracy to measure the time of arrival of particles produced at the CERN LHC with better than 30ps timing accuracy. In order to achieve the measurement precision, the reference clock that has to be distributed to multiple sites across the detector, has to have a better than 10ps phase alignment accuracy ⁷ .

Several critical parameters associated with the signal such as long-term accumulated jitter, clock slew rate, cycle to cycle jitter is crucial for the experiments to ensure an accurate and reliable event reconstruction. In particular, jitter is one of the main criteria used to specify and qualify electronics systems in detectors[4].

In this program , a custom radiation-hardened clock jitter cleaner system, with very low added jitter of <200>20 . This enables us to have wide margin of phase correction from 100 femtoseconds to 10’s of picoseconds or even more. Another important parameter in integrated clock generators is their supply sensitivity (as experienced by lpGBT chip as well). A combined effort between a low-noise power supply regulator, which is usually a linear low-dropout regulator, along with associated VCO supply sensitivity characteristics[5]. Figure 1 shows top level system of the proposed PLL based jitter cleaner ASIC and its application in a serial link suitable with high energy physics experiments[6].

The following innovations are going to be implemented in the proposed project:

• A wideband jitter cleaning PLL with a tuning range covering 40MHz to 10GHz frequency band[1]
• A fully integrated phase noise measurement module that is sensitive to -80dBc/Hz phase noise resolution at 100kHz offset ²⁰ .
• A low noise linear regulator, minimizing supply noise impact on VCO phase noise, achieving 10uVrms integrated noise from 100Hz to 1MHz

A low jitter PLL achieving less than 300 f _sec,rms additive jitter from 10kHz to 10MHz with integrated phase noise cancellation module. 

Technical Approach

Alphacore’s top level system approach is shown in Figure 1. The solution uses a two-way time-phase transfer approach where phase difference in each front end module (FEM) is measured and sent to central unit and vice versa. A reference pulse synchronous to the source edge is created in both central (master) unit and FEMs alternatively. The delay includes the drivers and receivers delay along with finite state machine’s (FSM) delay (Figure 1 right).

The two-way time-phase transfer system where a central (Master) single chip, multi-channel PSJC system talks to it’s counterpart PSJC system on each of the FEMs (the FEMs will have the PSJC system integrated and are considered as Slave systems). The central system (Master) keeps a record of all the phase deviations on each of the FEMs (Slaves) and periodically sends the phase error polarity (positive or negative) and magnitude to each of the FEMs. An average over time is measured for high accuracy of delay estimation. The phase error is calculated by round trip delay mechanism by both the FEM and the central system and is different for each FEM depending on each of their temperature of operation and distance from central system. The significance of this innovation is that the system can adjust/control the phase at front-end modules at sub-pico second resolution (as low as 200fs) using “delay-discriminator based feed-forward phase noise cancellation PLL” while consuming ultralow power, as needed in typical DOE FEMs. A high accuracy of synchronization is achieved because of

1. Accuracy of phase error estimation system (limited by only the jitter of source clock)
2. Ability to generate small phase delays in the PLL without adding any additional jitter using our delay discrimination

The system will be designed in TSMC 28nm which is inherently TID tolerant for up to 200Mrad. The system is highly digital in nature with inbuilt error correction which will make it SEU and SET tolerant than existing solutions (such as lpGBT ). SEL tolerance will be achieved by using Alphacore’s previously silicon proven layout strategies (such as our 130nm PLL). 

The phase delay counter (PD _M or PD _S , on master and slave module respectively in the equation in Figure 2), represented as delay counter (MPE/FEPE) in Figure 1 (b), is estimated using a interpolated-flash time-domain counter as shown in Figure 2 (a). The delay’s account for all the fixed and moving variables (such as temperature dependency of circuits in Master and FEM modules, T _M and T _S ). The accuracy is limited by the jitter in start and stop signals generated master and FEM’s PSJC systems (which is better than 200fs in this case). MtS _(M) denotes Master to Slave delay measured on Master Unit. Similarly StM _(S) denotes Slave to Master delay measured on Slave Unit. Inv _i (T _i ), where i is M or S for Master and Slave, is the unit’s internal inverter delay which is dependent on temperature of operation. Td1 and Td2 are round board level and cable level trip delays (from Master to Slave and Slave to Master). Since these operate at environment temperature (as opposed to ASIC chip junction temperature which could go up to 80C) the delays are largely considered constant values. The equations shown in Figure 2 (b) show the measured delays and that are stored in Master and Slave Units. Once these values are stored, they are sent to Master Unit.

The interpolated flash counter operates in an open loop unrolled fashion where each interpolation sub-counter flip-flop’s job is to trigger next flip-flop and auto reset immediately. This process starts as soon as its sub-counter delay clock is triggered. The sub-counter clock is shorted to MSB counter delay chain. This way, the sub-counters’ (2-bits each as shown in Figure 2a) flip-flop will be ready for next MSB clock pulse to restart counting and do not need any combinational logic dependent reset mechanism. The sub-counter counts as many times as it’s MSB clocks are triggered. Once the counter stops (with the Stop Signal), all counters are stopped and the last bit out of each level of counters (MSB counter and LSB sub-counters) are read and converted to proportional delay value. Reducing phase noise and jitter in high-performance, multi-node data and clock distribution systems is a critical requirement for the PSJC system to meet the performance. Often, a jitter attenuating clock ASIC or a phase-locked loop (PLL) is used to produce low jitter clocks. A traditional PLL architecture is comprised of a phase frequency detector (PFD), loop filter (LF) and voltage-controlled oscillator (VCO). One of the more challenging elements in designing with high-performance PLLs is how to choose the required loop bandwidth for a given application, to minimize the overall jitter.

The clock distribution jitter is categorized into two major components: generated jitter and additive jitter . A jitter attenuating PLL can be used to filter noise from the input clock and produce a low jitter output clock. Reducing the loop filter bandwidth increases the amount of jitter attenuation on the input clock, transferring less jitter from the input to the output. If the input clock has a significant amount of jitter, using a low PLL bandwidth to filter this noise is typically used. However, with a low bandwidth PLL VCO noise to a PLL's output jitter increases as the loop bandwidth decreases. A low PLL bandwidth can have the detrimental effect of increasing the output clock jitter, as shown in Figure 3 b. In a typical loop bandwidth PLL bandwidth needs to be set to minimize both VCO and reference jitter

Low jitter clock buffers are specified in terms of their additive jitter. For clock buffers and drivers, the clock source is the input signal, therefore the clock source jitter is not included for the buffers jitter specification. Additive jitter refers to the amount of phase jitter contributed by the clock driver, independent of its input clock jitter. One of the most critical contributors to clock buffer additive jitter is the supply noise (AM noise) converting into phase noise (PM noise).

In this project, we will also be designing low integrated noise linear low dropout (LDO) supply regulators suitable for clock generation and distribution circuitry. This is particularly a problem in LPGBT. In a typical clock jitter cleaning PLL and clock driver, most supply noise says the blocks are VCOs, and output drivers. As discussed earlier their noise and jitter characteristics are not shaped by the PLL loop bandwidth and they need to be either suppressed or canceled. shows the list of complex sub-systems/circuits that are most likely affected by different types of radiation and would have significant effect on the performance of the PLL.

The following sections are organized as follows: in section .A, an overview prior work on on-chip jitter measurement methods will be provided, followed by their application to jitter cleaning PLLs will be provided. In section B proposed jitter cleaning PLL and associated supply regulator topology will be introduced and target specifications will be provided.

Prior Work on Low-Jitter Clock Generation and Distribution:

Recent work in reducing phase noise and jitter in fully integrated SoCs focuses on dedicated supply regulation, adding bypass capacitors and improving thermal and 1/f noise profile of the PLL building blocks. As clock frequencies in the digital domain move higher into GHz range with sub-picosecond jitter margins, accurate on-chip phase noise/jitter measurement is becoming a valuable tool to measure and adaptively tune the PLL performance. The ability to measure and correct for systematic phase error problems presents a fundamental shift in the paradigm from relying on low noise cell level design to designing around leakier, noisy and less matched transistors in future technologies.

Jitter and phase noise correspond to different ways of representing undesired timing errors of a periodic signal. While phase noise is commonly used in RF systems to represent frequency or phase inaccuracy, jitter refers to sampling timing error or clock

edge uncertainty in digital or analog systems. From a measurement standpoint, phase noise remains the most accurate way of characterizing the performance of RF, analog and digital signal sources. Timing jitter can be measured either indirectly from phase noise by integrating the noise spectrum over a specified frequency range or directly using very high-speed sampling oscilloscopes. The direct measurement approach requires expensive test equipment and typically yields less accurate results compared to the indirect method since it is ultimately limited by the jitter of the external measurement clock. Phase noise measurement has so far been limited to off-chip methods using either spectrum analyzers or specialized test equipment. No on-chip phase noise measurement technique has been reported to date in the literature.

Voltage Control Oscillators (VCOs) are one of the most critical blocks in phase-locked loops (PLLs). LC-tank VCOs have a superior phase noise performance. However, they require bulky passive resonators and calibration to overcome their limited tuning range. Ring oscillator (RO) based VCOs are attractive for digital system applications owing to their ease of integration, small die area and scalability in deep submicron processes. However, due to their supply sensitivity and poor phase noise performance, they have limited use in applications demanding low phase noise floor, such as wireless or optical transceivers. Particularly, the out-of-band phase noise of RO-based PLLs is dominated by the RO noise floor, which cannot be suppressed by the loop gain. Wide loop bandwidth PLLs can suppress RO phase noise at higher frequencies; however, they suffer from increased in-band noise due to contributions generated by reference, phase-detector and charge-pump. Most phase noise cancellation schemes reported so far have been targeting deterministic SD modulator quantization noise in fractional-N synthesizers[1]. These approaches enable wider loop-bandwidths and cancel close-in phase noise due to quantization error in the fractional controller. However, they cannot track and cancel random phase errors in a PLL.

Recently, a feed-forward phase noise extraction and cancellation technique based on a delayed-discriminator phase detector is presented in [2]. The proposed circuit can attenuate the RO phase noise in an arbitrary band of interest. This approach can cancel both the ambient and inherent device noise without the need for on-line calibration. The cancellation path gain and bandwidth tracks process, voltage and temperature (PVT). Due to gain and bandwidth tracking, one time calibration is sufficient. The implemented noise-cancelling loop can enable RO-PLL based frequency synthesizers to be utilized in high sensitivity applications requiring low phase noise, such as broadband tuners and RF transceivers. We will utilize this method for a low-bandwidth clock jitter cleaning approach, to enable VCO noise contribution to the output clock jitterutilize this method for a low-bandwidth clock jitter cleaning approach, to enable VCO noise contribution to the output clock jitter. 

Radiation-hardened-by-design (RHBD) PLL and Clock Distribution

In order to make a robust design, it is very important for the PLL to remain in-lock for a wide temperature range. The oscillation frequency of a typical VCO will decrease as the temperature increases. Once the frequency drift is beyond the coverage of the tuning band, the PLL can lose lock. To avoid this kind of failure, a new LC-VCO temperature compensation scheme is developed to reduce the frequency drift. Unlike the conventional solutions ^{[1] [2] [3] [4]} , no redundancy in the LC-tank is needed and thus the tuning range and phase noise of the VCO will not be affected. Specifically, the VCO frequency dependency on its amplitude characteristics is employed to control the VCO amplitude such that it is inversely proportional to temperature, thus compensating the temperature-induced frequency drift.

 To make VCO amplitude inversely proportional to temperature, a CTAT biasing current is needed. Figure 5a shows the schematic of the proposing group’s previously designed PLL’s VCO biasing current generator. Combining PTAT and CTAT biasing currents, Ibias with sufficiently wide temperature coefficient can be generated.

In addition to temperature, radiation strikes can cause PLL to lose lock for a large number of clock cycles. The output node of the charge pump is the most Single-Event-Effect (SEE) sensitive node since it is directly connected to the loop filter where the VCO control voltage is generated. New radiation-hardened-by-design (RHBD) techniques are being developed to mitigate the SEE effect. Specifically, we have been developing a new SET-induced charge detection and compensation technique. This solution does not affect typical PLL design and dynamics. It can improve both SET-induced VCO control voltage perturbation and recovery time. A control block is included to avoid the conflict between SET-compensation and normal PLL phase correction.

The solution comes with reasonable power, area, and performance costs. The RHBD techniques used are illustrated in Figure 6. Three RHBD techniques are used in the PLL to eliminate and mitigate SEE. Firstly, all the sequential logic blocks are implemented by using DICE cell as indicated in the figure. For the DICE cell, its timing parameters will be optimized to make it immune to SET at its input. Secondly, unlike conventional PLL loops, this PLL will include two cross-coupled negative impedances for the LC-tank. The purpose of this dual redundancy is to mitigate SET inside the VCO. If an SET happens in one of the VCOs, the other will help to reduce the magnitude of the induced disturbance by a factor of two. The third RHBD technique is SET-detection and compensation (CC), which is used to mitigate SET at the most vulnerable node of the PLL, the charge pump output node. The SET-detection and compensation circuit consists of three sub-blocks, SET detector, compensator, and charge-compensation-controller (CCC). The SET detector includes two high-speed comparators, CMPP and CMPN, as well as their biasing circuitries. CMPP has a negative input offset voltage of -24 mV; while CMPN has a positive input offset voltage of +24 mV. This offset voltage is set based on a tradeoff between detection resolution and noise immunity, as well as implementation feasibility. The compensator comprises M1, M2, and two switches. The CCC is designed to guarantee that the compensator can be enabled only when VCP is hit by SET.

In normal operation, when the loop is locked and there is no SEE, CCC will turn on the switches in the compensator to make it standby so that it is able to react to SET whenever it happens. In this case, VCP is stable and the differential inputs of CMPP and CMPN are both zero.

Therefore, due to the input offsets, the output of CMPP will be ‘1’ and the output of CMPN will be ‘0’. As a result, compensation transistor M1 and M2 will be both turned off. PLL operation is not affected by CC. Once SET hits VCP, the voltage perturbation will be sensed and amplified by CMPP or CMPN. According to the polarity of the strike, either M1 or M2 will be turned on to compensate the injected charge. For instance, if a positive voltage perturbation is induced at VCP by SET, this high frequency perturbation will be coupled to the positive inputs of CMPP and CMPN through M3. If the coupled version is larger than the input offset of CMPN, its output will be asserted to ‘1’ and M2 will be turned on to sink the injected charge until VCP plunges back to its original value. During this process, the output of CMPP will stay at ‘0’ and thus M1 is turned off. This scheme, therefore, can limit the SET-induced VCP perturbations and reduce the recovery time. Besides, a third order loop filter is adopted to further purify the VCO control voltage (VVCO). The PLL was previously implemented in 0.13μm CMOS by the proposing group as shown in Figure 7

Measurements of the PLL tuning characteristics at the divide-by-2 output show that the PLL covers a frequency range from 5.6GHz to 13.4GHz. The overlap ratio is larger than 80%. The maximum Kvco is about 550MHz/V. The random jitter is measured to be 365fS at 5.72GHz divide-by-2 output at 25°C.

The PLL jitter performance is shown in Figure 8a. By using the proposed temperature compensation technique, the PLL can remain locked from -40°C to 125°C and less than 50fS integrated jitter variation is observed over temperature. The PLL consumes 50.88mW from a 1.2V supply at 12GHz at 25°C.

detectors, therefore it can withstand Total Ionizing Dose (TID) of 200 Mrad with Non Ionizing Energy Loss (NIEL) radiation of around ~1015 1 MeV neq/cm2. Its robust operation to SEUs is ensured Triple Modular Redundancy (TMR) used in the State Machines and the “low-frequency” section of the Data Path. An LC-VCO architecture for increased SEU-Tolerance and low jitter is utilized.

Our proposed jitter-cleaning PLL architecture utilizes a locking and low-phase delay between the reference and output clocks, and for delay synchronization, an additional programmable delay block could be utilized also.

PrXoposed Clock Phase Noise and Jitter Cleaning ASIC for Clock Generation and Distribution:

Active Noise Cancellation Jitter Cleaning PLL

As shown in Figure 10 (a), in a free-running RO, each variable delay cell exhibits random phase error due to device, supply and substrate noise. When the RO VCO is locked within a PLL, the phase error accumulation is filtered by the PLL dynamics. As shown in Figure 10 (b), the DC and low frequency components of the VCO control voltage determine the close-in phase noise. Within the PLL loop bandwidth, deviations of the VCO frequency is locked to the reference clock and is attenuated by the PLL loop gain. The phase noise of the VCO outside the PLL bandwidth is dominated by the RO’s noise floor characteristic and our approach tries to address noise performance in this region.

There are several techniques to measure the phase noise and jitter of integrated oscillators. In [1] , a delay line and mixer (i.e., delay-line discriminator) was used to convert the instantaneous phase deviations of an oscillator to voltage deviations, enabling an on-chip real-time phase noise measurement. This technique does not require a spectrally clean reference clock and can extract the phase noise for a wide range of frequency offsets from the carrier frequency. As shown in Figure 11, the proposed PLL utilizes a similar delay-line discriminator to measure the RO’s instantaneous phase noise in a selected bandwidth, and to cancel the phase noise with a voltage-controlled delay element outside the PLL. The delay element is matched with the VCO delays and tracks the PVT variations of the VCO.

As shown in Figure 11, a bandpass filter is required to suppress the cancellation path flicker noise. The highpass filter before the cancellation delay element allows the PLL to control the DC and low frequency VCO frequency shifts, which is important to set the steady state output frequency and reduce in-band phase noise. Therefore, in the proposed approach the PLL controls the steady state VCO frequency, while the cancellation path suppresses the far out phase noise. In order to achieve effective phase noise cancellation, the differential BPF output is inverted and applied to the auxiliary delay stage outside the PLL. In general, the VCO output phase without cancellation can be represented in time domain by:

The output of the cancellation delay cell becomes:

where K _aux is the auxiliary delay cell sensitivity in rads/volts. As discussed earlier the gain of the delay discriminator path is designed to match the delay characteristics of the main VCO. In a typical implementation, the VCO frequency gain is times greater than the individual delay cell voltage characteristics, which reduces the noise contributions of the feedforward path by. In this design the noise contribution of the feedforward path to an open-loop, un-cancelled VCO at 1MHz offset will be around 20dB lower than the VCO itself. The feedforward noise contribution is 12dB lower than the cancelled VCO, ensuring no significant noise impact on the overall VCO floor noise.

Conclusions and Target Specifications

A ring oscillator based PLL with active noise cancellation with integrated supply regulator and clock buffers will be designed with than 200 fsec,rms additive jitter from 10kHz to 10MHz with integrated phase noise cancellation module. The active noise cancellation circuit would measure and cancel the phase noise in a selected bandwidth by using a similar delay element as used in the main VCO. The feed-forward cancellation circuit tracks the process and temperature variations of the VCO delay element, requiring only a one time gain adjustment. The proposed approach can suppress several ambient noise sources also, such as supply and substrate noise. A 12 dB phase noise reduction is targeted achieved with only 35% increase in the VCO power and 17% increase in the overall PLL power.

Radiation Tolerance and Reliability

Radiation tolerance will be considered on both process and design levels in this PSJC system development. Alphacore has been closely following the test results of the TSMC 28nm process conducted by CERN. Alphacore representatives had long discussions about these results with Paulo Moreira during the TWEPP conference in 2018, and also during a phone call in the spring of 2019. We also keep close ties with Federico Faccio, who is responsible for the technology radiation testing at CERN.

Single event effects will need to be considered for logic circuits. To that end, we plan to apply circuit-, coding-, as well as system-level techniques to address the issue. First of all, dynamic logic gates should be completely avoided due to their SEU sensitivity. Next, dual interlocked storage cell (DICE) technique will be employed to protect all configuration registers on the chip. Any accumulated errors in registers will be removed by a periodic refreshing operation. Critical timing circuits such as the PLL and clock distribution network will be protected with TMR. For high-speed signal paths that cannot afford the speed penalty of TMR, we will identify the SEU-sensitive nodes and protect these nodes with redundancy circuits with low speed overhead. A quantitative measure of the trade-off between the SEU cross section, circuit size, and design overhead (i.e., area, power, and speed) needs to be assessed. Lastly, block- or system-level redundancy will also be explored for SEU detection and correction. In addition to these techniques, the Alphacore team “keeps an eye on” reported circuit sensitivities, as well as reported new hardening methods. One example is a single event hardening method for VCO PLLs presented at TWEPP (and at other venues as well).

Alphacore will use guard rings throughout the design to make the design immune to single event latchup (SEL). The topology will also be protected against potential single event functional interrupts (SEFI) by paying close attention to the single event response of the voltage references and the clock circuits, such as the PLL. Single event strikes in the voltage references have been shown to cause transients up to 600um in high-bandwidth ADCs that are otherwise immune to SEEs. [2] One mitigating technique is using clamp diodes to flush out the accumulated charge. [3]

Alphacore’s Dr. Mikkola has extensive experience in radiation hardening technology and he has published several references on radiation hardening of data converters [4] [5] [6] [7] . In February 2019, Alphacore has also hired Dr. Marek Turowski who has more than 20 years of experience in radiation effects and RHBD techniques, as well as more than 200 published papers on semiconductor devices. Alphacore also employs Dr. Yago Gonzalez-Velo who is an expert in radiation testing. Table 2 discusses some of Alphacore’s radiation effect testing and RHBD work and its relation to this program.

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