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IO System - Non-Synthesizable Verilog Model - Engineering Assignment Help
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Your testbench should efficiently generate a stimulus using tasks or functions as appropriate to create test sequences. Code should be easily readable with clear intent. The testbench should include a monitor module that models the desired FSM behaviour and reports errors between expected output and the DUT output. Your testbench’s error checking should be entirely automated and should produce a log file that reports pass/fail results.
Refer to Chu book section 7.5.10 and view the Comprehensive Testbench example on Blackboard for further information on the intended structure of this testbench.
Instructions
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Task: In Practical 1 you designed an FSM to maintain a carpark occupancy count. Recall that the FSM was monitoring activity of cars using two sensors, as pictured in Figure 1 below. The desired behaviour for this module was that the count would increase upon observation of a sensor sequence matching a car entering the carpark (sensor input ab = “00” ? “10” ? “11” ? “01”? ”00”), and decrease upon observation of a sensor sequence matching a car exiting the carpark (sensor input ab = “00” ? “01” ? “11” ? “10” ? ”00”). The carpark maximum occupancy was 15 vehicles. Need the code and FSM diagram for this question as well. For Practical 2, you must now develop a self-checking testbench that will instantiate the top-level of this FSM. Your testbench should use the same structure as in the Comprehensive Testbench example in the Chu book (see Figure 2).
Your testbench should efficiently generate a stimulus using tasks or functions as appropriate to create test sequences. Code should be easily readable with clear intent. The testbench should include a monitor module that models the desired FSM behaviour and reports errors between expected output and the DUT output. Your testbench’s error checking should be entirely automated and should produce a log file that reports pass/fail results.
Refer to Chu book section 7.5.10 and view the Comprehensive Testbench example on Blackboard for further information on the intended structure of this testbench.
Instructions
- Create modules for a top-level testbench, a stimulus generator to drive all inputs of the FSM and a monitor to receive FSM inputs and outputs and produce pass/fail results.
- Instantiate your DUT, stimulus generator and monitor modules in your top-level testbench. Connect the stimulus and DUT output in a similar manner to Figure 2.
- Complete the Verilog code for your stimulus generator and monitor blocks.
- Introduce errors into your FSM and report how your testbench reacts to them.
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