KD7020 - Modelling And Simulation of XADC Input Circuitry Report Writing - Engineering Assignment Help

Assignment Task

Assignment 1 – Modelling and Simulation of XADC input circuitry using the SMASH® mixed-signal

simulator Useful sources of information

• ‘7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide’ – document ‘ug480_7Series_XADC.pdf’

• ‘XAPP95 - Driving the Xilinx Analog-to-Digital Converter’ – document ‘xapp795-drivingxadc.

Task 2.1 – Open the ‘Test_XADC_input.nsx’ file using a suitable text editor (such as Notepad++) and complete the description, with the aid of figure 2.1. Initially, omit components R1 and CA (by commenting out), and comment out the pulse voltage source ‘VP1’. The timing parameters are as follows:

Taqu = 1us, Thold = 7us, Tsample = 10us;

The first initial block in the net-list description of Appendix A creates the repetitive digital stimulus for the ‘cap_sample’ and ‘cap_reset’ digital signals. Insert statements into the body of the forever loop in order to create the waveforms .

Task 2.2 – Open the net-list file (.nsx) with the SMASH software and correct any syntax errors that may arise. Select the top-level module and set up a transient analysis to run for 100 us, with a print step of 10 ns. Run the simulation (you may need to click on the run button twice to get the ‘Simulation finished’ message to appear). Add the following waveform traces to the Transient window and zoom out to the full extent. 

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