NEE3104 - Digital Combinational Circuits Simulation Using Multisim - Engineering Assignment Help

Assignment Task

 Theory 

In this lab we will study the basic logic gates and acquire understanding of the fundamentals of  combinatorial logic circuits. The lab will investigate the design of simple combinational circuits  using National Instruments (NI) Multisim. 

Basics of Digital Logic  

Digital logic circuits are designed to perform logic operations on one or more binary inputs to  generate one or more binary outputs. Binary inputs or outputs are signals represented by one of  two levels – HIGH or LOW signal levels. Logic HIGH is also referred to as binary ‘1’ and logic  LOW is also referred to as ‘0’. There are two major representations of binary signal levels 

depending on the technology used to implement the internals of logic circuits. These are the  Complementary metal–oxide–semiconductor (CMOS) and the Transistor-Transistor Logic (TTL). 

Characteristics of CMOS logic: 

•  Voltage levels range from 0 to VDD where VDD is the supply voltage. A low level is  anywhere between 0 and 1/3 VDD while a high level is between 2/3 VDD and VDD. ? Dissipates low power: The power dissipation is dependent on the power supply voltage,  frequency, output load, and input rise time. At 1 MHz and 50 pF load, the power dissipation  is typically 10 nW per gate. 
•  Short propagation delays: Depending on the power supply, the propagation delays are  usually around 25 ns to 50 ns. 
•  Rise and fall times are controlled: The rise and falls are usually ramps instead of step  functions, and they are 20 - 40% longer than the propagation delays. 
•  Noise immunity approaches 50% or 45% of the full logic swing. 
•  Levels of the logic signal will be essentially equal to the power supplied since the input  impedance is so high. 

•  Voltage levels range from 0 to Vcc where Vcc is typically 4.75V - 5.25V. Voltage  range 0V - 0.8V creates logic level 0. Voltage range 2V - Vcc creates logic level 1. ? Power dissipation is usually 10 mW per gate. 
•  Propagation delays are 10 nS when driving a 15 pF/400 ohm load. 

CMOS compared to TTL: 

•  CMOS circuits do not draw as much power as TTL circuits while at rest. However,  CMOS power consumption increases faster with higher clock speeds than TTL does.  Lower current draw requires less power supply distribution, therefore causing a simpler  and cheaper design. 
•  Due to longer rise and fall times, the transmission of digital signals becomes simpler and  less expensive with CMOS chips. 
•  CMOS components are more susceptible to damage from electrostatic discharge than  TTL components. 

Logic Gates 

Logic gates constitute the foundation blocks for digital logic. Let us start by reviewing these  gates and their truth tables: 

An AND Gate has two or more inputs and produces one output as follows: output = 1 if all of the  inputs are high, output = 0 if one or more of the inputs are low. 

An OR gate also has two or more inputs and produces one output as follows: output = 1 if one or  more inputs are high, output = 0 if all inputs are low:

The NAND gate has two or more inputs and produces one output as follows: output = 0 if all the  inputs are high, output = 1 if any of the inputs are low. 

Fig. 4 

The NOR gate has two or more inputs and produces one output as follows: output = 1 if all  inputs are low, output = 0 if any of the inputs is high.

Table 1 Truth table  

Inputs Outputs  

1. Write the Boolean logic functions for outputs F1 and F2 in the sum of products (SOP) form. 2. What state is missing? What is a “don’t care” state? 

3. Design a logic circuit for the truth table given in Table 1. 

4. Does the circuit in Fig. 8 represent any of the outputs (F1 or F2)? If so which one? 5. If you only have digital logic gates with a maximum of two inputs, how will you construct the circuit in Fig. 8? 

6. Construct the circuits for both F1 and F2 in National Instruments Multisim using suitable  AND, OR and NOT gates. Connect the three inputs to a 5 V source through a switch pack as  shown in Fig 8. Here the switch positions determine the input logic level (i.e., 0 V for logic  ‘0’ and 5 V for logic ‘1’. Connect each output to the positive terminal of an LED and connect  the negative terminal of the LED to ground. Observe the LED state to verify the circuit  operates according to the truth table. 

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