NME3508 - CAD of Multiplier - Engineering Assignment Help

Assignment Task

1) CAD of multiplier

i) Design a digital circuit that will read a 5-bit binary number (D4, D3, D2, D1, D0) and multiply it by 21, generating a 10-bit result.

The report in your logbook should include:

• Your design considerations

• ANNOTATED circuit schematics and layouts

• Some conclusions on the use of CAD and simulation

• Some thoughts on possible implementations

2) Implement the schematic in Altera and simulate your design using appropriate input codes for the following circuits.

a) Design a 2 x 4-bit array multiplier.

b) Design a 2 x 4-bit sequential multiplier.

c) Design a 2 x 4-bit sequential divider.

3) Design a FSM schematic that will output a pulse of 1 clk duration after it has detected 101 input sequence:

a) Implement your schematic in Altera.

b) Simulate your design: Initialise to ‘0’ on start-up and apply the input sequence 01110101, noting the condition of the output.

4) Design a circuit that when triggered will produce an output pulse of two clock cycles duration, but not trigger unless the original trigger has been removed. Implement the design in Altera;

a) Using basic FSM design technique

b) Generic Implementation using Flip-Flops and ROMs

c) Generic Implementation using Flip-Flops and multiplexers

d) Simulate your designs.

5) Sketch outline designs for a circuit that will detect the sequence 101B, wait two clock cycles, then generate a pulse on output A, and a further two clock cycles later a pulse on output B. Implement your design in Altera;

a) Using one-hot coding

b) Multiple FSMs

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