Pipe-lining on a RISC Architecture - IT Assignment Help

Assignment Task

1. Objectives
This project is designed to help students to understand the pipelining on a RISC architecture (MIPS), pipeline hazards, and hazards mitigation techniques including forwarding and stalling. Students will gain programming experience in C.
2. Goals
Your team of 2 students will build a simulator of a (5-stage pipelined) MIPS in C. This simulator will read a binary executable file containing a sequence of MIPS instructions and simulate their execution in stages in a (pipelined) MIPS processor.
Project 1 is a non-pipelined MIPS.
Project 2 is a pipelined MIPS without the considerations for branch hazard and data forwarding.
Project 3 is a pipelined MIPS including branch hazard and data forwarding.
3. Specification
3.1 Input
Your simulator will read a binary executable file. It is of size 1KB and consists of 512B of data segment followed by 512B of text segment (offset 0x200). Do not try to open this file as it causes an error. You can view a binary file using od command in linux (e.g., od -Ax -t x4 memory.out) or format-hex command in Windows Powershell (e.g., format-hex memory.out). Assume input files do not contain any errors.
3.1.1 Registers
The user can use any of the 32 MIPS registers (0-31). Please note that $0 is read-only and should always contain the value 0. Your simulator will need to include a register file (e.g., an array of 32 integers) that maintains the values of all the 32 registers and updates the registers as the 

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