Pipe Ports - Engineering Assignment Help

Assignment Task -                 
 

Stage II

The next step is to write a module idexwb_pipe that accepts the following ports, in this order

As the name implies, this stage does instruction decode, execute and write back. This computer has just four instructions: nop, add, mul and addi. The binary opcodes are provided on the top of the file proc.v. This module instantiates about 9 yMux modules to redirect signas an add_pipe to execute add and addi and a mul_pipe to execute mul. It also instantiates an rfile register file to sote and retrieve results. Name the instance of rfile  "regs", othewise the testbench will not work.

Hints

At every clock cycle this module updates register Rdout in rfile. Since it gets an Rdout from the add_pipe and one from mult_pipe it only saves the one that is non zero. When a mul instruction is executed the add_pipe module gets a 5-bit zero as Rdin and the mul_pipe gets Rd. The opposite happens for an add or an addi instruction. When the instruction is mul or add the contents of Rs2 is used as a second input to the respective module, whereas if it is an addi the immediate imm is given as a second input. Submit file proc.v. To test your code use the testbench provided and compile with iverilog -o test testidexwb.v proc.v. Make sure that your program works for at least the testbench provided.

Stage III

Create a module if_pipe that has the following ports:

Use module predecode in the file provided to do the decoding. This module handles the ugly details of the instruction formats. In the module if_pipe define an array imem of at least 64 32-bit registers to serve as instruction memory and a WIDTH-bit resgister PC. During the reset the following command should be executed: $readmemb("compmem.dat", imem, 6'd0, 6'd22); to load the memory with data. You have to download compmem.datin the directory you are working so that the testbench can find it.

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