Programmable Square-Wave Generator - FPGA Design Flow - Integrated Logic Analyzer ILA - Engineering Assignment Help

Assignment Task:

Programmable Square-Wave Generator Engineering Assignment Help

Task Description:

 • A programmable square-wave generator is a circuit that can generate a square wave with variable ON (i.e., logic 1) and OFF (i.e., logic 0) intervals. The duration of the intervals is specified by two 4-bit control signals, m and n, which are interpreted as unsigned integers.  

• The ON and OFF intervals are m ×10 ns and n×10 ns, respectively (recall that the period of the onboard oscillator is 10 ns).

• Design a programmable square-wave generator circuit. The circuit should be completely synchronous.  

• Use Vivado ILA to verify the operation (else you require a logic analyser).  

• You may use the DIP/PUSH switches or VIO for giving the m and n inputs.  

• In order to verify the output, always generate the reference “clock/2” (20ns) as output and tap it using ILA. Your output can be verified against the reference clock.

You need to carry out all FPGA design flow steps and test the design using ILA. A physical logic analyzer is simply a digital system that samples various probes and displays the signal. Since generally not all the gates are used in an FPGA, why not use parts of the FPGA to synthesize a logic analyzer? That's exactly an Integrated Logic Analyzer ILA. Full feature edition of Vivado allows you to view your actual signals in your design with a synthesized logic analyzer. To view the signals, additional signals are place and routed but used internally to display the waveforms. Obviously, to run, your design must synthesize and loaded to the FPGA. Two reference videos links on ILA are mentioned below. You need to submit a report in a similar format as was informed during assignment 1. The simulation results should be shown for both pre and post-ILA simulations. 

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