Highlights
OBJECTIVES:
Understand the operation of a successive-approximation ADC and an R/2R ladder DAC
Build an R/2R ladder DAC and test it with a 4-bit binary counter
Design and build a successive-approximation ADC using an R/2R DAC
You prepare for conversion by resetting the successive-approximation register (SAR) to zero. Conversion is done by testing each bit of the SAR: set a bit HIGH; convert the resulting digital number stored in the SAR to analog using a DAC; compare its analog output with the analog input (Vin) that is to be converted to digital. Conversion is complete when all bits of the SAR are tested. Detailed procedure is as follows:
Reset SAR to zero.
Test one bit of SAR at a time by setting it HIGH, starting from D7 (MSB)
3) DAC converts the SAR content to analog (Vout)
Comparator compares V+ (Vout) with V- (Vin) and produces a HIGH output when V+ ≥ V-.
Modify the logic state of the bit being tested depending on the comparison result:
If the result = 0, then Vin is smaller (that is, if the digital value in the SAR is too large). Thus, clear the bit;
else leave the bit set at 1;
once properly modified, you are done with this bit. You DO NOT change this bit again.
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