Verilog Code - Computer Science Assignment Help

Assignment Task:

1) 4%    The following code describes an 8 bit ___NAND___ Gate:
input [7:0] A;
output Z;
assign Z = (A != 255);

2) 6%    Consider the following code, describe 3 critical issues with it, or rules broken.

  input In;
  output Out;
  reg[1:0] State, Next;      
  reg A; 
  wire D;
  always @(*) begin
    case(State)
     0: Next = In?1:0; 
     1: Next = In?2:0; 
     2: Next = In?1:1; 
    Endcase
    D <= In && A;
    A  = D ^ In;
  end
  always @(posedge Clk) begin
    State <= Next; 
    if (State != 1) A <= In; Out <= 0;
  end      

Any statement before = or <= in an always block should be defined reg type,
D <= In && A; will cause a syntax error because it is a wire type.Wire types are used in assign statements so the following lines of code are all written in correctly:
wire D; //has to be changed to reg D;
D <= In && A;
D has to be a reg type to be in an always block, wire is used in continuous statements.

Second syntax error Endcase is endcase not Endcase, Verilog is case sensitive. 

Clk is not declared anywhere.

There is no module name declaring the input and output ports. 

if (State != 1) A <= In; Out <= 0; //Procedural assignment error, Out has to be a reg type to be in a procedural assignment. Have to declare: output reg Out;
3) 20%    Finish writing the Verilog code for an 8-bit Encoder. In is an 8-bit value, when New is true, Out should be the LSB of In. Then on the next posedge Clk, output should be the second LSB of In. After the MSB is output, Out should become zero and stay that way until the next New = true.

module Encode8(Clk, In, New, Out);
    input Clk;
input[7:0] In;
    input New;
    output Out;
    reg[2:0] bit;

end module
4) 25%    Absolute Summer; Write a Verilog module that has inputs Clk, Clr, and In; with outputs Sum and Saturated. In is an 8-bit signed value, each cycle the absolute value of In is added to Sum (an 8-bit unsigned value). When Clr is true, Sum is set to the absolute value of In. If Sum >= 255, Sum = 255 and Saturated is true. You must use a premade 8-bit full adder module full8add (a, b, c_in, c_out, sum), do not use ‘+’.

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