VHDL Implementation of AES Algorithm for LOT Security Assignment

Assignment Task

Background

Advanced Encryption Standard (AES) the latest encryption standard approved by NIST is by far becoming the default choice for encryption in networked applications. FPGA-based Hardware implementation of the algorithm gives better performance but offers less flexibility and is also difficult and time-consuming to implement as compared to a software implementation.

Aims

My objective is to implement the Advanced Encryption Standard algorithm on hardware using a Hardware Description Language. The preferred HDL is VHDL. A fully Synthesizable Register Transfer Level (RTL) code will be written using VHDL to implement the encryption and decryption modules. The design will be optimized for the three constraints i.e area, timing, and power.

Objective

The VHDL-based AES encryption and decryption design will be simulated for accuracy and performance using a VHDL test bench. The area, timing, and power summary will be evaluated to evaluate the overall performance.

Main Methods

The design will be simulated using the VIVADO Design Suite.

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