VLSI Interconnect Minimization - Engineering Assignment Help

Assignment Task

Digital electronics inception started based on magnetically controlled switches (or relays), they were mainly used in the implementation of very simple logic circuit which would not catch up with time, digital electronic computing started in full with the introduction of the vacuum tube which were originally used almost exclusively for analog processing but later it was discovered that the vacuum tube could also be implemented for digital computations as well, and its integration was in its thousands implying low performance with also a high power consumption downside. From then It became obvious that this switching ability and its integration density design technology has reached its climax.

Creative minds of semiconductors engineers based on the physical and chemical behavior of semiconductors, engineers were able to come up with the transistor of various types all based on the concepts of controlling the channel connecting an input to an output, ranging from the BJT to MOSFET to other possible better candidates that may replace this current transistor technology.

Performance in integrated circuits is the major factor put in consideration and over the years engineers have worked on ways to improve it, starting from the scalability side engineers had to create invent the BJT as a better switching technology to vacuum tubes also as applications grows and more performance are needed the MOSFET was invented with better scalability ability, just for having performance increase by scaling down circuit element to contain more circuit element on a chip, and have been improved from SSI (small scale integration) chips were the gate count was small in its hundreds to MSI (medium scale integration) chips in its thousands gates to LSI(large scale integration) chips in its tens of thousands to VLSI (very large scale integration) chips in its millions and the shrinking of the MOSFET continues to get more tending

towards nano technology. However, there is a trade off as the number of transistors that can be fabricated on a single chip is continuously increasing with the rapid advances and improvements in VLSI technology combined with the continuous shrinkage in the chip feature size has led to very high chip densities, keeping pace with these advancements switching speeds are also have led to increase in interconnect delay which is directly proportional to the length of the interconnect between transistors. Thus, arises the essential need for efficient interconnect routing algorithms used by routers in EDA (electronic design automation tools), minimizing the length of interconnects is the only way to reduce the interconnect delay since the width of interconnects and other feature parameters are assumed to be fixed, to achieve the minimum interconnect length becomes the main task of any efficient routing algorithm.

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